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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 117 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Equivalent Elmore Delay for RLC Trees
 Proceedings of the ACM/IEEE Design Automation Conference
, 2000
"... Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specif ..."
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Cited by 39 (8 self)
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Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specifically, the complexity of calculating the time domain responses at all the nodes of an tree is linearly proportional to the number of branches in the tree and the solutions are always stable. The closedform expressions introduced here consider all damping conditions of an circuit including the underdamped response, which is not considered by the Elmore delay due to the nonmonotone nature of the response. The continuous analytical nature of the solutions makes these expressions suitable for design methodologies and optimization techniques. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for trees can be practically used for the same purposes that the Elmore delay is used for trees.
Fitted elmore delay: A simple and accurate interconnect delay model
 In Proceedings of the IEEE International Conference on Computer Design, IEEE Computer Society Press, Los Alamitos, CA
, 2002
"... In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay model. Thus our model has all the advantages ..."
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Cited by 26 (0 self)
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In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay model. Thus our model has all the advantages of the Elmore delay model. It has a closed form expression as simple as the Elmore delay model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the Elmore delay model. In fact, most previous algorithms and programs based on Elmore delay model can use our model without much change. Most importantly, FED is significantly more accurate than the Elmore delay model. The maximum error in delay estimation is at most 2 % for our model, compared to 8.5 % for the scaled Elmore delay model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than Elmore delay model when applied to wire sizing. 1.
Simultaneous buffer and wire sizing for performance and power optimization
 in Proc. Int. Symp. on Low Power Electronics and Design
, 1996
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More Practical BoundedSkew Clock Routing
 J. VLSI SIGNAL PROC
"... Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, risetime and overshoot constraints, obstacle and legal locationchecking, varying layer parasitics and congestion, and even the underlying des ..."
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Cited by 14 (1 self)
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Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, risetime and overshoot constraints, obstacle and legal locationchecking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying layer parasitics with nonzero via parasitics; (ii) obstacleavoidance clock routing; (iii) a new topology design rule for prescribeddelay clock routing; and (iv) predictive modeling of the clock routing itself. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches.
PlanarDME: A singlelayer zeroskew clock tree router
 IEEE Trans. Comput. Aid. Des. Integ. Circ. Syst
, 1996
"... This paper presents new singlelayer, i.e., planarembeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called PlanarDME, consists of two parts. The rst algorithm, calledLinearPlanarDME, guarantees an optimal planar zeroskew clo ..."
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Cited by 8 (2 self)
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This paper presents new singlelayer, i.e., planarembeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called PlanarDME, consists of two parts. The rst algorithm, calledLinearPlanarDME, guarantees an optimal planar zeroskew clock tree (ZST) under the linear delay model. The second algorithm, called ElmorePlanarDME, uses the LinearPlanarDME connection topology in constructing a lowcost ZST according to the Elmore delaymodel. While a planar ZST under the linear delay model is easily converted to a planar ZST under the Elmore model by elongating tree edges in bottomup order, our key idea is to avoid unneeded wire elongation by iterating the DME construction of ZST and the bottomup modi cation of the resulting nonplanar routing. Costs of our planar ZST solutions are comparable to those of the best previous nonplanar ZST solutions, and substantially improve over previous planar clock routing methods. 1
Minimizing Wirelength in Zero and Bounded Skew Clock Trees
, 1999
"... An important problem in VLSI design is distributing a clock signal to synchronous elements in aVLSI circuit so that the signal arrives at all elements simultaneously. The signal is distributed by means of a clock routing tree rooted at a global clock source. The difference in length between the long ..."
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Cited by 7 (0 self)
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An important problem in VLSI design is distributing a clock signal to synchronous elements in aVLSI circuit so that the signal arrives at all elements simultaneously. The signal is distributed by means of a clock routing tree rooted at a global clock source. The difference in length between the longest and shortest rootleaf path is called the skew of the tree. The problem is to construct a clock tree with zero skew (to achieve synchronicity) and minimal sum of edge lengths (so that circuit area and clock tree capacitance are minimized). We give the first constantfactor approximation algorithms for this problem and its variants that arise in the VLSI context. For the zero skew problem in general metric spaces, we give an approximation
A DeepSubmicron Steiner Tree
"... . ATree is a rectilinear Steiner tree in which every sink is connected to a driver by a shortest length path, while simultaneously minimizing total wire length. This paper presents a polynomial approximation algorithm for the generalized version of ATree problem with upperbounded delays along eac ..."
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Cited by 1 (0 self)
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. ATree is a rectilinear Steiner tree in which every sink is connected to a driver by a shortest length path, while simultaneously minimizing total wire length. This paper presents a polynomial approximation algorithm for the generalized version of ATree problem with upperbounded delays along each path from the driver to the sinks and with restrictions on the number of Steiner nodes. We refer to it as "Deepsubmicron Steiner tree" as minimizing the number of Steiner nodes is crucial for signal integrity issues in deepsubmicron verylargescaledintegratedcircuit (VLSI) designs. The idea behind the algorithm is to control two parameters in order to construct a feasible (with respect to the paths delays and the number of Steiner nodes) tree of small cost. The simulation results show the high efficiency of our approach. 1 Introduction With the scaling of device technology to deep submicron dimension, gate delay is getting faster by device scaling factor S and scaled wires increase d...
UsefulSkew Clock Routing With Gate Sizing for Low Power Design
"... Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost ..."
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Instead of zeroskew or assuming a xed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skewmay allow a larger timing budget for gate sizing. We construct a usefulskew tree (UST) such that the total clock and logic power(measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree congurations. This is complemented by a bipartitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11 % to 22 % total power reduction over previous methods of clock routing with zeroskew or single xed skew bound and separately sizing logic gates. 1
c ° 1997 Kluwer Academic Publishers. Manufactured in The Netherlands. Practical BoundedSkew Clock Routing⁄
, 1996
"... Abstract. In Clock routing research, such practical considerations as hierarchical buffering, risetime and overshoot constraints, obstacle and legal locationchecking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in ..."
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Abstract. In Clock routing research, such practical considerations as hierarchical buffering, risetime and overshoot constraints, obstacle and legal locationchecking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying layer parasitics with nonzero via parasitics; (ii) obstacleavoidance clock routing; and (iii) hierarchical buffered tree synthesis. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches. 1. Preliminaries Control of signal delay skew has become a dominant objective in the routing of VLSI clock distribution networks and large timingconstrained global nets. Thus, the “zeroskew ” clock tree and performancedriven routing literatures have seen rapid growth over the past several years; see [1, 2] for reviews. “Exact zero skew” is typically obtained at the expense of increased wiring