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An event spacing experiment
 In Proceedings of the Eigth International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 2002
"... timing analysis This memo is a paper submitted to Async 2002. Here’s the abstract from the next page: We describe our investigation into the spacing of events in selftimed rings. All rings that we have seen previously produce bursts of events. These bursts are caused by “drafting,” the dependence o ..."
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Cited by 22 (5 self)
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timing analysis This memo is a paper submitted to Async 2002. Here’s the abstract from the next page: We describe our investigation into the spacing of events in selftimed rings. All rings that we have seen previously produce bursts of events. These bursts are caused by “drafting,” the dependence of the delay of a gate on the time since its previous output event. We present a simple model for drafting based on the Charlie Diagrams of [5]. We use these models to identify the causes of bursts and to propose a method to control bursting behaviour. Based on this analysis, we have designed, fabricated, and tested a chip where event spacing can be switched between bursting and evenly spaced events according to an externally applied reference current. This is the first reported chip where a selftimed ring achieves evenly spaced events. x[N1] C C
The Role of BackPressure in Implementing LatencyInsensitive Systems
 Electronic Notes in Theoretical Computer Science
, 2006
"... Backpressure is a logical mechanism to control the flow of information on a communication channel of a latencyinsensitive system (LIS) while guaranteeing that no packet is lost. Backpressure is necessary for building open LISs and it represents an interesting design alternative also for closed LI ..."
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Cited by 9 (1 self)
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Backpressure is a logical mechanism to control the flow of information on a communication channel of a latencyinsensitive system (LIS) while guaranteeing that no packet is lost. Backpressure is necessary for building open LISs and it represents an interesting design alternative also for closed LISs because it makes possible to realize highly modular implementations with more predictable features in terms of design overhead (area, power). In discussing the role of backpressure, we revisit the logic of the necessary building blocks, and explain the impact of the system topology on the system performance.
Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets
 Hardware Design and Petri Nets
, 1999
"... . This paper describes and extends a recently developed approach for performance analysis of asynchronous circuits modeled with stochastic timed Petri nets (STPNs) with unique and freechoice places and arbitrary delay distributions. The approach analyzes finite STPN executions to derive closedfor ..."
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Cited by 7 (0 self)
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. This paper describes and extends a recently developed approach for performance analysis of asynchronous circuits modeled with stochastic timed Petri nets (STPNs) with unique and freechoice places and arbitrary delay distributions. The approach analyzes finite STPN executions to derive closedform expressions for lower and upper bounds on the performance estimates that can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds thus provides an estimate of the performance metric which has a welldefined error interval. Moreover, we can often make the error interval arbitrarily small by analyzing longer STPN executions at the cost of additional runtime. Experiments on several asynchronous systems demonstrate the high quality of our estimates and the efficiency of the technique. The experiments include the performance analysis of a fullscale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID...
Accelerating Markovian Analysis of Asynchronous Systems using Stringbased State Compression
 IEEE Transactions on ComputerAided Design
, 1998
"... This paper presents a methodology to speed up the stationary analysis of large Markov chains that model asynchronous systems. Instead of directly working on the original Markov chain, we propose to analyze a smaller Markov chain obtained via a novel technique called stringbased state compression. O ..."
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Cited by 6 (4 self)
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This paper presents a methodology to speed up the stationary analysis of large Markov chains that model asynchronous systems. Instead of directly working on the original Markov chain, we propose to analyze a smaller Markov chain obtained via a novel technique called stringbased state compression. Once the smaller chain is solved, the solution to the original chain is obtained via a process called expansion. The method is especially powerful when the Markov chain has a small feedback vertex set, which happens often in asynchronous systems. Experimental results show that the method can yield reductions of more than an order of magnitude in run time and facilitate the analysis of larger systems than possible using traditional techniques. 1 Introduction Driven by market demands for lowpower and highperformance, tools to estimate power and performance of a system have become particularly important. In an asynchronous system, the randomness caused by varying input data rate and data proce...
Comparison of tree and straightline clocking for long systolic arrays
 Journal of VLSI Signal Processing
, 1991
"... Abstract. A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straightline clocking. We present ..."
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Cited by 5 (0 self)
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Abstract. A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straightline clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the tradeoffs between reliability and throughput in both schemes. Our basic conclusion is that as the onedimensional systolic array gets very long, tree clocking becomes more reliable than straightline clocking. 1.
Symbolic Time Separation of Events
 In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1999
"... We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the c ..."
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Cited by 4 (0 self)
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We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are 1) an iterative algorithm which continuously narrows down the domain of interest and 2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know. 1. Introduction This paper presents a novel approach to timing analysis based on a new paradigm we refer to as "symbolic timing verif...
Temporal Properties of SelfTimed Rings
 In proceedings of CHARME 2001, Lecture Notes in Computer Science 2144
, 2001
"... Various researchers have proposed using selftimed networks to generate and distribute clocks and other timing signals. We consider one of the simplest selftimed networks, a ring, and note that for timing applications, selftimed rings should maintain uniform spacing of events. ..."
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Cited by 4 (1 self)
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Various researchers have proposed using selftimed networks to generate and distribute clocks and other timing signals. We consider one of the simplest selftimed networks, a ring, and note that for timing applications, selftimed rings should maintain uniform spacing of events.
Using Synchronized Transitions for Simulation and Timing Verification
 Workshop on Designing Correct Circuits
, 1991
"... Synchronized Transitions is a formal notation for hardware specification, verification, and simulation. This paper describes the use of Synchronized Transitions in the design of a chip for high bandwidth interprocessor communication. The chip uses a hybrid of synchronous and selftimed circuit te ..."
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Cited by 2 (1 self)
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Synchronized Transitions is a formal notation for hardware specification, verification, and simulation. This paper describes the use of Synchronized Transitions in the design of a chip for high bandwidth interprocessor communication. The chip uses a hybrid of synchronous and selftimed circuit techniques; a proof is presented that all timing requirements are satisfied. The Synchronized Transitions notation is presented, and it is shown how programs can be translated into logic predicates, providing a basis for formal verification. The use of Synchronized Transitions in the simulation of the chip is described, and the design choices of using both simulation and formal proofs are discussed.
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays
, 2002
"... Finding time separation of events is a fundamental problem in the analysis of asynchronous systems. When component delays have statistical variations, it is both interesting and useful to compute moments of time separation of events. Traditionally, Monte Carlo simulation has been used for this purpo ..."
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Cited by 2 (1 self)
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Finding time separation of events is a fundamental problem in the analysis of asynchronous systems. When component delays have statistical variations, it is both interesting and useful to compute moments of time separation of events. Traditionally, Monte Carlo simulation has been used for this purpose. However, Monte Carlo simulation requires knowledge of the probability distributions of component delays, which is often difficult to ascertain. Much more easily available are parameters like the statistical mean and variance of component delays. Unfortunately, with only these parameters, Monte Carlo simulation cannot be reliably applied. Yet another disadvantage of Monte Carlo simulation is the large number of runs needed before the error term becomes small enough to be acceptable. This paper describes a polynomialtime algorithm for computing bounds on the first two moments of times of occurrence of events in an acyclic timing constraint graph, given only means and variances of component delays. We present experimental results demonstrating the effectiveness of our algorithm.
Performance Estimation and Slack Matching for Pipelined Asynchronous Architectures with Choice
"... Abstract — This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the problem of pipelining “slack matching. ” The approach targets systems with hierarchical topologies, which typically ..."
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Cited by 2 (2 self)
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Abstract — This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the problem of pipelining “slack matching. ” The approach targets systems with hierarchical topologies, which typically result when highlevel (block structured) language specifications are compiled into datadriven circuit implementations. A significant contribution is that our approach is the first to efficiently handle architectures with choice (i.e., the presence of conditional computation constructs such ifthenelse and conditional loops). The key idea behind the fast speed of our analysis method is to exploit information about the hierarchy of a given blockstructured system, thereby yielding a runtime that is linear in the number of pipeline stages. In contrast, existing approaches typically represent an entire system as a single Petri net or marked graph, and then apply Markov chain analysis or other state enumeration methods with costly runtimes. Building upon our analysis approach, we introduce a novel solution to the problem of slack matching, i.e., determining optimal insertion of FIFO stages into a pipelined design to improve performance. We present both an optimal solution using an MILP formulation, and a fast heuristic algorithm that yielded optimal results for all of our examples. I.