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40
An Efficient Optimizationbased Technique to Generate Posynomial Performance Models for Analog Integrated Circuits
 in: Proc. 39th Design Automation Conf., Ernest Morial Convention
, 2002
"... This paper presents an new directfitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient geometric programming techniques for circuit ..."
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This paper presents an new directfitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient geometric programming techniques for circuit sizing and optimization. The automatic generation avoids the timeconsuming nature and inaccuracies of handcrafted analytic model generation. The technique is based on the fitting of posynomial model templates to numerical data from SPICE simulations. Attention is paid to estimating the relative `goodnessoffit' of the generated models. Experimental results illustrate the significantly better accuracy of the new approach.
Automated design of operational transconductance amplifiers using reversed geometric programming
 In Proceedings of the 41th IEEE/ACM Design Automation Conference
, 2004
"... We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimizati ..."
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We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimization, without compromising global optimality. These constraints allow increased accuracy for critical modeling equations, such as the relationship between gm and IDS. To demonstrate the design methodology, a foldedcascode amplifier is designed in a 0.18 µm technology for varying speed requirements and is compared with simulations and designs obtained from geometric programming. Categories and Subject Descriptors:
Generalized Posynomial Performance Modeling
 IN DATE ’03
, 2003
"... This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with devicelevel a ..."
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This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with devicelevel accuracy. We will prove that this problem corresponds to solving a nonconvex optimization problem without local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the timeconsuming nature of handcrafted analytic model generation. Experimental results illustrate the capabilities and effectiveness of the presented modeling technique.
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics
 In Proceedings Design Automation and Test in Europe Conference
, 2002
"... This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a templatebased fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the genera ..."
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This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a templatebased fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative `goodnessoffit' of the generated expressions. Experimental results illustrate the capabilities of the approach.
CMOS Operational Amplifier Design and Optimization via Geometric Programming
 IN PROCEEDINGS OF THE FIRST INTERNATIONAL WORKSHOP ON DESIGN OF MIXEDMODE INTEGRATED CIRCUITS AND APPLICATIONS
, 1997
"... We describe a general method for optimized design of CMOS operational amplifiers. We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a spec ..."
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We describe a general method for optimized design of CMOS operational amplifiers. We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence, we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs between competing performance measures such as power, openloop gain, and bandwidth. Our method, therefore, yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications. In this
Constructing generalized mean functions using convex functions with regularity conditions
 SIAM J. Optim
"... Abstract. The generalized mean function has been widely used in convex analysis and mathematical programming. This paper studies a further generalization of such a function. A necessary and sufficient condition is obtained for the convexity of a generalized function. Additional sufficient condition ..."
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Abstract. The generalized mean function has been widely used in convex analysis and mathematical programming. This paper studies a further generalization of such a function. A necessary and sufficient condition is obtained for the convexity of a generalized function. Additional sufficient conditions that can be easily checked are derived for the purpose of identifying some classes of functions which guarantee the convexity of the generalized functions. We show that some new classes of convex functions with certain regularity (such as S∗regularity) can be used as building blocks to construct such generalized functions. Key words. Convexity, mathematical programming, generalized mean function, selfconcordant functions, S∗regular functions. AMS subject classifications. 90C30, 90C25, 52A41, 49J52
Optimal doping profiles via geometric programming
 IEEE Transactions on Electron Devices
, 2005
"... Abstract—We first consider the problem of determining the doping profile that minimizes base transit time in a (homojunction) bipolar junction transistor. We show that this problem can be formulated as a geometric program, a special type of optimization problem that can be transformed to a convex op ..."
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Abstract—We first consider the problem of determining the doping profile that minimizes base transit time in a (homojunction) bipolar junction transistor. We show that this problem can be formulated as a geometric program, a special type of optimization problem that can be transformed to a convex optimization problem, and therefore solved (globally) very efficiently. We then consider several extensions to the basic problem, such as accounting for velocity saturation, and adding constraints on doping gradient, current gain, base resistance, and breakdown voltage. We show that a similar approach can be used to maximize the cutoff frequency, taking into account junction capacitances and forward transit time. Finally, we show that the method extends to the case of heterojunction bipolar junction transistors, in which the doping profile, as well as the profile of the secondary semiconductor, are to be jointly optimized. Index Terms—Base doping profile, base transit time minimization, cutoff frequency maximization, geometric programming, Geprofile optimization, optimal doping profile. I.
"Conefree" primaldual pathfollowing and potential reduction polynomial time interiorpoint methods
 MATH. PROG
, 2005
"... We present a framework for designing and analyzing primaldual interiorpoint methods for convex optimization. We assume that a selfconcordant barrier for the convex domain of interest and the Legendre transformation of the barrier are both available to us. We directly apply the theory and techni ..."
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We present a framework for designing and analyzing primaldual interiorpoint methods for convex optimization. We assume that a selfconcordant barrier for the convex domain of interest and the Legendre transformation of the barrier are both available to us. We directly apply the theory and techniques of interiorpoint methods to the given good formulation of the problem (as is, without a conic reformulation) using the very usual primal central path concept and a less usual version of a dual path concept. We show that many of the advantages of the primaldual interiorpoint techniques are available to us in this framework and therefore, they are not intrinsically tied to the conic reformulation and the logarithmic homogeneity of the underlying barrier function.
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
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Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1
MacroDriven Circuit Design Methodology for HighPerformance Datapaths
 in Proc. of ACM/IEEE DAC
, 2000
"... Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite o ..."
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Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite of this, very little automation has been available to the designers of high performance datapaths. In this paper we present a new "macrodriven " approach to the design of datapath circuits. Our approach, referred to as SMART (Smart Macro Design Advisor), is based on automatic generation of regular datapath components such as muxes, comparators, adders etc., which we refer to as datapath macros. The generated solution is based on designer provided constraints such as delay, load and slope, and is optimized for a designer provided cost metric such as power, area. Results on datapath circuits of a highperformance microprocessor show that this approach is very effective for both designer productivity as well as design quality.