Results 11  20
of
29
DeltaSigma Data Conversion in Wireless Transceivers
, 2002
"... Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wirel ..."
Abstract

Cited by 4 (2 self)
 Add to MetaCart
Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.
Segmented Dynamic Element Matching for HighResolution DigitaltoAnalog Conversion
"... Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require lowresolution but highlinearity DACs. More recently, segmented DEM architectures have made highresolution Nyquistrate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. Index Terms—Digitaltoanalog conversion, dynamic element matching (DEM), segmentation. I.
PhaseNoise Cancellation Design Tradeoffs in DeltaSigma FractionalN PLLs
 IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing
, 2003
"... Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop ..."
Abstract

Cited by 4 (2 self)
 Add to MetaCart
Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop bandwidth that can be achieved by PLLs incorporating the technique are quantified. Design guidelines are derived that enable customization of the technique in terms of PLL target specifications. Index Terms—Delta–sigma modulator, fractional PLL, phasedlocked loop (PLL), segmented digitaltoanalog converter (DAC), synthesizer. I.
Quadrature Mismatch Shaping for DigitaltoAnalog Converters
"... Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise i ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to nearperfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the wellknown butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient firstorder QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance. Index Terms—Butterfly shuffler, mismatch shaping, quadrature bandpass (QBP), treestructured, 61 analogtodigital converters (ADCs). I.
Joint Spatial and Temporal DeltaSigma Modulation for Wideband Antenna Arrays and Video Halftoning
"... Extending an existing architecture for deltasigma conversion of vector inputs, we suggest spectrally shaping quantization noise jointly in temporal and spatial frequency domains with deltasigma modulation, and we examine the application of the idea to wideband antenna or acoustic arrays and to hal ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
Extending an existing architecture for deltasigma conversion of vector inputs, we suggest spectrally shaping quantization noise jointly in temporal and spatial frequency domains with deltasigma modulation, and we examine the application of the idea to wideband antenna or acoustic arrays and to halftoning of video imagery. 1.
A 14bit 10MSamples/s D/A Converter Using Multibit  Modulation
 IEEE Journal of SolidState Circuits
, 1999
"... Abstract — A 14bit digitaltoanalog converter based on a fourthorder multibit sigma–delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6bit output of this modulator is converted to analog using 64 currentsteering ce ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
Abstract — A 14bit digitaltoanalog converter based on a fourthorder multibit sigma–delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6bit output of this modulator is converted to analog using 64 currentsteering cells that are continuously calibrated to a reference current. This converter achieves 85dB dynamic range at 5MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5"m CMOS technology and operates from a single 2.5V supply. Index Terms — Current calibration, digitaltoanalog conversion, mixed analog–digital integrated circuits, multibit modulators, pipelined adders, sigma–delta modulation. I.
A Digital CommonMode Rejection Technique for Differential AnalogtoDigital Conversion
, 2001
"... A multibit analogtodigital converter can achieve high resolution with a lower order and lower oversampling ratio than a singlebit design, but it requires a multibit internal flash analogtodigital converter rather than a simple comparator. In an implementation with a fully differential ana ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
A multibit analogtodigital converter can achieve high resolution with a lower order and lower oversampling ratio than a singlebit design, but it requires a multibit internal flash analogtodigital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analogtodigital converter must quantize a differential voltage relative to a set of differential reference voltages. Though analog techniques for differential analogtodigital conversion exist, implementing them in a lowvoltage singlepoly CMOS process is a challenging circuit design problem. This paper presents a digital commonmode rejection technique for differential analogtodigital conversion (ADC), which avoids the circuit complexity and die area requirements of analog commonmode rejection techniques. This technique was used to implement the internal quantizer in two highperformance singlepoly CMOS ADC prototypes with over 98dB peak signaltonoiseanddistortion ratio and 105dB spuriousfree dynamic range. Implementation details, die area requirements, and measured commonmode rejection are presented for the prototype. Signalprocessing details of digital commonmode rejection within the modulator are presented, showing that injected commonmode noise results only in modulation of the quantization error power and does not create spurious tones.
A tight signalband power bound on mismatch noise in a mismatch shaping digitaltoanalog converter
 IEEE Trans. Inf. Theory
, 2004
"... Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signaltonoise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatchshaping DACs exploit builtin redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatchshaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatchshaping DAC: the dithered firstorder lowpass treestructured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dcfree sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signalband DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analogtodigital, data converters, dcfree sequences, delta–sigma (16), digitaltoanalog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.
Quadrature Mismatch Shaping with a Complex, Tree Structured DAC
 in IEEE International Symposium on Circuits and Systems, ISCAS
, 2006
"... Abstract — Quadrature bandpass (QBP) Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with nearperfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that sh ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
Abstract — Quadrature bandpass (QBP) Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with nearperfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic elementmatching (DEM) techniques. To select the unit DAC elements of the complex multibit DAC, the wellknown data directed swapper is generalized towards a complex structure and the necessary constraints for its correct functioning are derived. Additionally, a hardware efficient structure is presented: the reduced butterfly shuffler. Here, some of the QBP swapper cells are replaced by bandpass (BP) swapper cells. Also, great attention is paid to the interconnection pattern of the data directed swapper to prevent instability. I.
A digital requantizer with shaped requantization noise that remains well behaved after nonlinear distortion
 IEEE Trans. Signal Process
, 2007
"... Abstract—A major problem in oversampling digitaltoanalog converters and fractional frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals pa ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Abstract—A major problem in oversampling digitaltoanalog converters and fractional frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a new method of digital requantization called Successive Requantization, special cases of which avoids the spurious tone generation problem. Sufficient conditions are derived that ensure certain statistical properties of the quantization noise, including the absence of spurious tones after nonlinear distortion. A practical example is presented and shown to satisfy these conditions. Index Terms—Dither techniques, nonlinearities, quantization. I.