Extending an existing architecture for delta-sigma conversion of vector inputs, we suggest spectrally shaping quantization noise jointly in temporal and spatial frequency domains with delta-sigma modulation, and we examine the application of the idea to wideband antenna or acoustic arrays and to halftoning of video imagery. 1.

Abstract — A 14-bit digital-to-analog converter based on a fourth-order multibit sigma–delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-"m CMOS technology and operates from a single 2.5-V supply. Index Terms — Current calibration, digital-to-analog conversion, mixed analog–digital integrated circuits, multibit modulators, pipelined adders, sigma–delta modulation. I.

A multibit analog-to-digital converter can achieve high resolution with a lower order and lower oversampling ratio than a single-bit design, but it requires a multibit internal flash analog-to-digital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analog-to-digital converter must quantize a differential voltage relative to a set of differential reference voltages. Though analog techniques for differential analog-to-digital conversion exist, implementing them in a low-voltage single-poly CMOS process is a challenging circuit design problem. This paper presents a digital common-mode rejection technique for differential analog-to-digital conversion (ADC), which avoids the circuit complexity and die area requirements of analog common-mode rejection techniques. This technique was used to implement the internal quantizer in two high-performance single-poly CMOS ADC prototypes with over 98-dB peak signal-to-noise-and-distortion ratio and 105-dB spurious-free dynamic range. Implementation details, die area requirements, and measured common-mode rejection are presented for the prototype. Signal-processing details of digital common-mode rejection within the modulator are presented, showing that injected common-mode noise results only in modulation of the quantization error power and does not create spurious tones.

High-performance analog-to-digital converters, digital-to-analog converters, and fractional- frequency synthesizers based on delta--sigma (16) modulation---collectively referred to as data converters---have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.

Abstract — Quadrature bandpass (QBP) Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic elementmatching (DEM) techniques. To select the unit DAC elements of the complex multibit DAC, the well-known data directed swapper is generalized towards a complex structure and the necessary constraints for its correct functioning are derived. Additionally, a hardware efficient structure is presented: the reduced butterfly shuffler. Here, some of the QBP swapper cells are replaced by bandpass (BP) swapper cells. Also, great attention is paid to the interconnection pattern of the data directed swapper to prevent instability. I.

Abstract—Quadrature sigma–delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-toanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the well-known butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient first-order QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance. Index Terms—Butterfly shuffler, mismatch shaping, quadrature bandpass (QBP), tree-structured, 61 analog-to-digital converters (ADCs). I.

Abstract—A major problem in oversampling digital-to-analog converters and fractional- frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a new method of digital requantization called Successive Requantization, special cases of which avoids the spurious tone generation problem. Sufficient conditions are derived that ensure certain statistical properties of the quantization noise, including the absence of spurious tones after nonlinear distortion. A practical example is presented and shown to satisfy these conditions. Index Terms—Dither techniques, nonlinearities, quantization. I.

Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in delta-sigma data converters which require low-resolution but high-linearity DACs. More recently, segmented DEM architectures have made high-resolution Nyquist-rate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. Index Terms—Digital-to-analog conversion, dynamic element matching (DEM), segmentation. I.

Abstract—Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analog-to-digital, data converters, dc-free sequences, delta–sigma (16), digital-to-analog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.

Abstract approved: