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55
A 1.8V digitalaudio sigmadelta modulator in 0.8µm CMOS
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D con ..."
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Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D conversion that operates from a single 1.8V power supply. A cascaded modulator that maintains a large fullscale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fullydifferential switchedcapacitor integrators employing different input and output commonmode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of commonmode levels, high power supply noise rejection, and low power dissipation are obtained through the use of twostage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8μm CMOS technology with metaltopolycide capacitors and NMOS and PMOS threshold voltages of +0.65V and –0.75V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5 V to 2.5 V, occupies an active area of 1.5 mm 2, and dissipates 2.5 mW from a 1.8V supply.
TimeInterleaved Oversampling A/D Converters: Theory and Practice
 IEEE Trans. Circuits Syst. II
, 1997
"... In this paper, the design procedure and practical issues regarding the realization of timeinterleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary 16 topologies can be converted into corresponding timeinterleaved structures. Prac ..."
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Cited by 28 (4 self)
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In this paper, the design procedure and practical issues regarding the realization of timeinterleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary 16 topologies can be converted into corresponding timeinterleaved structures. Practical issues such as finite opamp gain, mismatching, and dc offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discretecomponent prototype of a secondorder timeinterleaved 16 analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented. Index TermsConverters, timeinterleaved, oversampling. I. INTRODUCTION O VERSAMPLING converters have become a popular technique for data conversion [1]. One reason for their popularity is their outstanding linearity which comes from the fact that they usually exploit a 1b quantizer. Even with a tr...
Onfocalplane signal processing for currentmode active pixel sensors
 IEEE Transactions on Electron Devices
, 1997
"... Abstract — Onfocalplane signal processing for currentmode active pixel sensors (APS), including fixed pattern noise (FPN) suppression and highresolution analogtodigital conversion (ADC), is presented. An FPN suppression circuit that removes the offset current variation between pixels by using ..."
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Abstract — Onfocalplane signal processing for currentmode active pixel sensors (APS), including fixed pattern noise (FPN) suppression and highresolution analogtodigital conversion (ADC), is presented. An FPN suppression circuit that removes the offset current variation between pixels by using a combination of an ntype and a ptype current copier cell is described. The FPN suppression circuit exhibits linear transfer characteristics in the input current range from 0 to 30 &quot;A. Onchip ADC is expected to improve imaging system performance and reliability, while reducing system size, weight, and cost. Operation and performance of a currentmode secondorder incremental 16 A/D converter with column parallel architecture and for highresolution and mediumslowspeed applications is presented. A 12bit resolution with 61.5 LSB accuracy at the conversion rate of 5.6 kHz was obtained. The LSB corresponds to less than twelve signal charges of currentmode 10&quot;m pixel APS’s. Based on the experimental results, a brief description of a possible image sensor with the onchip signal processing is also described. I.
Adaptive digital correction of analog errors in MASH ADCs. I. Offline and blind online calibration
 IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, 2000
"... Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect ..."
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Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finiteimpulse response (FIR) filters, of which the coefficients are determined through adaptive offline or online calibration. Of particular interest is an online “blind ” calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dualquantization oversampled converters demonstrate nearperfect adaptive correction and significant improvements in signaltoquantizationnoise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative online adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper [1]. Index Terms—Adaptation, analogtodigital conversion, blind
Design of a lowlightlevel image sensor with an onchip sigmadelta analogtodigital conversion
 in CCDs and Outical Sensors 111, Proc. SPIE
"... The design of a lowlightlevel CMOS activepixelsensor (APS) with onchip, semiparallel analogtodigital (A/D) conversion is presented. The imager consists of a 128x128 array of active pixels at a 50 im pitch. Each column of pixels shares a 10bit A/D converter based on firstorder oversampled s ..."
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The design of a lowlightlevel CMOS activepixelsensor (APS) with onchip, semiparallel analogtodigital (A/D) conversion is presented. The imager consists of a 128x128 array of active pixels at a 50 im pitch. Each column of pixels shares a 10bit A/D converter based on firstorder oversampled sigmadelta (>z) modulation. The 10bit outputs of each converter are multiplexed and read out through a single set of outputs. A semiparallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 10 e rms noise performance. A 28x28 activepixelsensor (APS) with 40x40p.tm2 pixels as well as individual elements of the sigmadelta modulator have been fabricated and tested using MOSIS * 2 m CMOS technology. 1.
An agile ISM band frequency synthesizer with builtin GMSK data modulation
 IEEE J. Solidstate Circuits
, 1998
"... Abstract — In this paper, a highresolution fractionalN RF frequency synthesizer is presented which is controlled by a fourthorder digital sigma–delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigm ..."
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Abstract — In this paper, a highresolution fractionalN RF frequency synthesizer is presented which is controlled by a fourthorder digital sigma–delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma–delta quantized tap coefficients is included which provides builtin GMSK pulse shaping for data transmission. Quantization of the tap coefficients to singlebit values not only simplifies the filter architecture, but the fourthorder digital sigma–delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple offchip loop filter and VCO required. The synthesizer operates from a single 3V supply, and has low power consumption. Phase noise levels are less than 90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than 90 dBc/Hz over a 19.6MHz tuning range. Index Terms — Frequency synthesizer, GMSK modulation, sigma–delta modulation, sigma–delta quantized tap coefficients, radio transmitters. I.
Jouanne, “Use of sigmadelta modulation to control emi from switchmode power supplies
 IEEE Trans. Ind. Elect
, 2001
"... Abstract—Conducted electromagnetic interference (EMI) is a major cause of concern in switchmode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, Sigma–Delta (61) modulation is proposed as an alternative switching technique to reduce conducted EMI from a ..."
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Abstract—Conducted electromagnetic interference (EMI) is a major cause of concern in switchmode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, Sigma–Delta (61) modulation is proposed as an alternative switching technique to reduce conducted EMI from an SMPS. The result of using 61 modulation is a spread in the spectrum of the conducted emissions so that large concentrations of power at discrete frequencies are avoided. Experimental timedomain waveforms and spectra of the switching function of firstorder and secondorder 61 modulators are presented to prove the viability of the scheme for EMI mitigation. These modulators are then applied to a dc–dc converter in an offtheshelf computer power supply and experimental results show a reduction of roughly 5–10 dB V in EMI emissions over standard PWM modulators. Index Terms—Electromagnetic compatibility, electomagnetic conducted interference, Sigma–Delta modulation, switchmode
LowPower decimation filter design for multistandard transceiver applications
, 1997
"... Recent efforts in the design of wireless RF transceivers focus on high integration and multistandard operation. Higher integration can be obtained by using receiver architectures, such as wideband IF with double conversion (WIF), that perform channel select filtering onchip at baseband. Performin ..."
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Recent efforts in the design of wireless RF transceivers focus on high integration and multistandard operation. Higher integration can be obtained by using receiver architectures, such as wideband IF with double conversion (WIF), that perform channel select filtering onchip at baseband. Performing this baseband channel select filtering in the digital domain allows for the programmability necessary to adapt to the different channel bandwidths, sampling rates, and CNR requirements of multiple communication standards. At the back of a widedynamic range sigmadelta modulator, a decimation filter can select a desired channel in the presence of both strong adjacent channel interferers and quantization noise from the digitization process. A lowpower decimation filter that performs channel select filtering for the GSM (European cellular) and DECT (European cordless) standards is presented. Automatic gain control is used within the filter to reduce the dynamic range and power consumption. Since the two standards have different blocking profiles and CNR i
ThreeChannel Correlation Analysis: A New Technique to Measure Instrumental Noise of Digitizers and Seismic Sensors
"... Abstract This article describes a new method to estimate (1) the selfnoise as a function of frequency of threechannel, linear systems and (2) the relative transfer functions between the channels, based on correlation analysis of recordings from a common, coherent input signal. We give expressions ..."
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Abstract This article describes a new method to estimate (1) the selfnoise as a function of frequency of threechannel, linear systems and (2) the relative transfer functions between the channels, based on correlation analysis of recordings from a common, coherent input signal. We give expressions for a threechannel model in terms of power spectral densities. The method is robust, compared with the conventional twochannel approach, as both the selfnoise and the relative transfer functions are extracted from the measurements only and do not require a priori information about the transfer function of each channel. We use this technique to measure and model the selfnoise of digitizers and to identify the frequency range in which the digitizer can be used without precaution. As a consequence the method also reveals under which conditions the interpretation of data may be biased by the recording system. We apply the technique to a Quanterra Q4120 datalogger and to a Network of Autonomously Recording Seismographs (NARS) datalogger. At a sampling rate of 20 samples/sec, the noise of the Q4120 digitizer is modeled by superposition of a flat, 23.6bit spectrum and a 24.7bit spectrum with 1/f 1.55 noise. For the NARS datalogger the noise level is modeled by superposition of a 20.8bit flat spectrum and a 23.0bit spectrum with 1/f 1.0 noise. The measured gain ratios between the digitizers in the Q4120 datalogger, smoothed over a tenth of a decade between 0.01 Hz and 8 Hz for data sampled with 20 samples/sec, are within 1.6 % (or 0.14 dB) of the values given by the manufacturer. Finally, we show an example of seismic background noise observations at station HGN as recorded by both an STS1 and a STS2 sensor. Between 0.01 and 0.001 Hz the vertical STS2 noise levels are 10–15 dB above the STS1 observations. The Quanterra Q4120 digitizer noise model enables us to exclude the contribution of the digitizer noise to be responsible for this difference.
LSB Dithering in MASH Delta–Sigma D/A Converters
"... Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can ..."
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Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither’s contribution to the power spectral density of the multistage digital 16 modulator’s output. A large class of popular multistage digital 16 modulators that satisfy the conditions are identified and tabulated for easy reference. Index Terms—Delta–sigma (16) modulation, dither techniques, MASH, quantization. I.