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An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
 IEEE Transactions on ComputerAided Design
, 1993
"... this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of ..."
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Cited by 117 (20 self)
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this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 17 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
HighPerformance CMOS System Design Using Wave Pipelining
, 1995
"... Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for ..."
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Cited by 7 (0 self)
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Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for virtual data storage. Wave pipelining of combinational circuits has been shown to achieve clock rates 2 to 7times those possible for the same circuits with conventional pipelining. Conventional pipelined systems allow data to propagate from a register through the combinational network to another register prior to initiating the subsequent data transfer. Thus, the maximum operating frequency is determined by the maximum propagation delay through the longest pipeline stage. Wave pipelined systems apply the subsequent data to the network as soon as it can be guaranteed that it will not interfere with the current data wave. The maximum operating frequency of a wave pipeline is therefore determ...
VLSI circuit performance optimization by geometric programming
 Annals of Operations Research
"... Abstract. Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show tha ..."
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Abstract. Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem considering delay, chip area and power dissipation can be reduced to unary geometric programs. We present a greedy algorithm to solve unary geometric programs optimally and efficiently. When applied to VLSI circuit component sizing, we prove that the runtime of the greedy algorithm is linear to the number of components in the circuit. In practice, we demonstrate that our unarygeometricprogram based approach for circuit sizing is hundreds of times or more faster than other approaches.
Architecture Evaluator's Work Bench and and its Application to Microprocessor Floating Point Units
, 1995
"... This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FU ..."
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Cited by 2 (2 self)
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This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FUPA incorporates four aspects of AEWB  latency, cost, technology and profiles of target applications. FUPA models latency in terms of delay, cost in terms of area, and profile in terms of percentage of different floating point operations. We utilize submicron device models, interconnect models, and actual microprocessor scaling data to develop models used to normalize both latency and area enabling technologyindependent comparison of implementations. This report also surveyed most of the state of the art microprocessors, and compared them utilizing FUPA. Finally, we correlate the FUPA results to reported SPECfp92 results, and demonstrate the effect of circuit density on FUPA implementations. ...
A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized
 CMOS and BiCMOS circuits,” in Proc. EURODAC
, 1994
"... This paper presents the first reported discrete gate sizing method to jointly include library optimization capability. The method enables a designer to find the best set of sizes to include in a library and study the tradeoff between the number of gate sizes in a library and circuit peTformance. Co ..."
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Cited by 1 (0 self)
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This paper presents the first reported discrete gate sizing method to jointly include library optimization capability. The method enables a designer to find the best set of sizes to include in a library and study the tradeoff between the number of gate sizes in a library and circuit peTformance. Compared with continuous sizing, discrete sizing with library optimization, achieves within 270 speed performance using 2X to 5X fewer cells in gbit adders. buffers. This capability is useful when optimizing a BiCMOS technology logic circuit since a BiCMOS gate can typicallly be modeled as a buffered CMOS gate [63. 1
A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic
"... Abstract — This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered ga ..."
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Abstract — This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered gates is made. In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fanout are identified and replaced with a lower power unbuffered (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lowerbound delay value that is calculated. Experimental results have confirmed the efficiency and utility of the proposed method. In 8b adder or 8 8 b multiplier networks, just two iterations are sufficient to achieve a delay that is at worst within 0.6 % of its final optimized value and at worst within 10 % of the lowerbound value. In the design of BiCMOS networks, it is seen that a speed advantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BiCMOS gates versus using all CMOS or all BiCMOS gates and that this advantage increases with the tightness of the power constraint and with load capacitance. Index Terms — Buffer insertion, combinational logic circuits, gate sizing, optimization methods. I.
Minflotransit: MinCost Flow Based Transistor Sizing Tool
, 2000
"... This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool that has two alternating phases. For a circuit with V transistors and E wires, the first phase (Dphase) is based on mi ..."
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This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool that has two alternating phases. For a circuit with V transistors and E wires, the first phase (Dphase) is based on minimum cost network flow, which in our application, has a worstcase complexity of O(V Elog(log(V ))). The second