Results 1 
4 of
4
An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
 IEEE Transactions on ComputerAided Design
, 1993
"... this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of ..."
Abstract

Cited by 91 (19 self)
 Add to MetaCart
this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
Abstract

Cited by 17 (1 self)
 Add to MetaCart
A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
HighPerformance CMOS System Design Using Wave Pipelining
, 1995
"... Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for ..."
Abstract

Cited by 6 (0 self)
 Add to MetaCart
Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for virtual data storage. Wave pipelining of combinational circuits has been shown to achieve clock rates 2 to 7times those possible for the same circuits with conventional pipelining. Conventional pipelined systems allow data to propagate from a register through the combinational network to another register prior to initiating the subsequent data transfer. Thus, the maximum operating frequency is determined by the maximum propagation delay through the longest pipeline stage. Wave pipelined systems apply the subsequent data to the network as soon as it can be guaranteed that it will not interfere with the current data wave. The maximum operating frequency of a wave pipeline is therefore determ...
Architecture Evaluator's Work Bench and and its Application to Microprocessor Floating Point Units
, 1995
"... This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FUPA in ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FUPA incorporates four aspects of AEWB  latency, cost, technology and profiles of target applications. FUPA models latency in terms of delay, cost in terms of area, and profile in terms of percentage of different floating point operations. We utilize submicron device models, interconnect models, and actual microprocessor scaling data to develop models used to normalize both latency and area enabling technologyindependent comparison of implementations. This report also surveyed most of the state of the art microprocessors, and compared them utilizing FUPA. Finally, we correlate the FUPA results to reported SPECfp92 results, and demonstrate the effect of circuit density on FUPA implementations. ...