This paper presents a formal technique for system-level power/performance analysis that can help the designer to select the right platform starting from a set of target applications. By platform we mean a family of heterogeneous architectures that satisfy a set of architectural constraints imposed to allow re-use of hardware and software components. More precisely, we introduce the Stochastic Automata Networks (SANs) as an effective formalism for average-case analysis that can be used early in the design cycle to identify the best power/performance figure among several application-architecture combinations. This information not only helps avoid lengthy profiling simulations, but also enables efficient mappings of the applications onto the chosen platform. We illustrate the features of our technique through the design of an MPEG-2 video decoder application.

This paper addresses an emerging new field of research that combines the strengths and capabilities of electronics and textiles in one: electronic textiles, or e-textiles. E-textiles, also called Smart Fabrics, have not only "wearable" capabilities like any other garment, but also local monitoring and computation, as well as wireless communication capabilities. Sensors and simple computational elements are embedded in e-textiles, as well as built into yams, with the goal of gathering sensitive information, monitoring vital statistics and sending them remotely (possibly over a wireless channel) for further processing. Possible applications include medical (infant or patient) monitoring, personal information processing systems, or remote monitoring of deployed personnel in military or space applications. We illustrate the challenges imposed by the dual textile/electronics technology on their modeling and optimization methodology.

Recent evolution in system-on-chip (SOC) design methodology demonstrates an important omission of a design principle that directly contributes to the success of conventional computer systems: the use of a simple programming model to separate application from architecture. In an effort to restore the powerful concept of programming in the context of system-on-chip, in this work we propose a new programming model, called context-flow, that is general-purpose, simple, safe, highly parallelizable yet transparent to the underlying architectural details. A high-performance SOC platform architecture is then designed to support this programming model, while fully exploiting the physical proximity between the processing elements. Using an architectural exploration framework with a multi-processor simulator, our case studies on real life applications demonstrate the feasibility of adapting imperative C programs to context-flow programs, as well as the performance efficiency of our context-flow architecture over bus-based and packet-switch-based alternatives. Finally, we propose an analytical performance model, based on queueing networks, for the new SOC platform architecture that is simple, synthesis-friendly, and as flexible and powerful as queueing theory.