It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC’s. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X.

In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying specific test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not affect static power dissipation. We also discuss how faults may be detected with a frequency domain analysis. In many cases, the Fourier spectra of the power supply currents in the good and faulty circuits will be very different. Power monitoring is also verified experimentally, for an example circuit. 1 Introduction Monitoring the current drawn from the power supply is one method to test a CMOS circuit [2--4]. In this paper, we demonstrate that monitoring the dynamic power dissipation of a device can also aid in fault detection. A fault which affects functionality also changes the energy consumption on input transitions. The inputs can be applied so as to maximize the difference in e...

We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constraint. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benchmark circuits. Simulation results show that a 17% reduction of average CPU time is achieved when performing simulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.

It is assumed that tests generated using the single stuck-at fault model will implicitly detect the vast majority of fault-causing defects within logic elements. This may not be the case. In this paper we characterize the possible shorts in the combinational cells in a standard cell library. The characterization includes errors on the cell outputs, errors on the cell inputs, and excessive quiescent current. The characterization provides input vectors to stimulate these errors. After characterizing the faults that occur due to possible electrical shorts, we compare the coverage of the logic faults using a single stuck-at test set and tests developed specifically to detect these shorts. We discuss the effectiveness of I DDQ testing for these faults. 1 Introduction A large percentage of the physical area of any complex CMOS logic chip is used to implement the individual logic gates; internal shorts in the logic gates may not be detected by single line stuck-at faults (SSA). The standard...

It was recently observed that, in order to improve the defect coverage of a test set, test generation based on fault models such as the single-line stuck-at model may need to be augmented so as to derive test sets that detect each modeled fault more than once. In this work, we report on test pattern generators for combinational circuits that generate test sets to detect each single line stuck-at fault a given number of times. Additionally, we study the effects of test set compaction on the defect coverage of such test sets. For the purpose of experimentation, defect coverage is measured by the coverage of surrogate faults, using a framework proposed earlier. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction if the test set is computed using appropriate test generation objectives. Moreover, two test sets generated using the same test generation objectives, except that compaction heuristics were used during the generation of one but not the other, typically have similar defect coverages, even if the compacted test set is significantly smaller than the noncompacted one. Test generation procedures and experimental results to support these claims are presented.

Currently, in most fault simulators physical defects have to be modeled as stuck-at faults in networks of primitive gates such as AND, NAND, etc. On the other hand, the inadequacy of the stuck-at fault model for today's technologies has been pointed out by many authors. In this paper, a compiler driven fault simulator is presented which handles arbitrary combinational faults. The set of basic cells and their fault models are not coded into the algorithm but can be specified by the user in a library. It is shown that this increased flexibility, which is obtained by cell instead of line oriented fault injection, does not degrade the performance of the simulator but, in contrast, results in a considerable speed-up (up to factor 40). 1 Introduction As has been observed by many authors a large amount of the physical defects typical of today's VLSI technologies can not be correctly modeled by stuck-at faults [BART82, BA83, GCV80, LA83]. In order to overcome this problem, techniques are unde...

Abstract A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules. This paper discusses the implementation ofcomparators which are self-testing with respect to faults caused by any single physical defect likely to occur inNMOS andCMOS integrated circuits. A new fault model for PLA's is presented. This model reflects several physical defects in VLSI circuits which are not accounted for in previously published models. It is shown that in a self-testing comparator, implemented as a single two-levelNOR-NORPLA, the number of required product terms grows exponentially with the number of input bits. A particular design of a comparator using a single two-levelNOR-NORPLA is discussed. The operation of this comparator under the faults in the fault model is analyzed in detail. The comparator is proven to be self-testing with respect to any likely single fault in the proposed fault model, provided that several guidelines about its physical layout are followed. The use of this comparator as a basic building block of fault-tolerant systems is discussed. Index Terms-Concurrent error detection, duplication and matching, faults in VLSI circuits, MOS PLA fault model, programmable logic array, self-testing comparator, two-rail code checker. I.

Automated fault diagnosis based on the stuckat fault model is not always e#ective. This paper presents practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design. Results are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.

This paper considers the fault detection problem for a single fault in a single MOS channel-connected subcircuit. We identify the following three decision sub-problems : (i) decide if a test vector exists; (ii) decide if an initializing vector exists; and (iii) decide if a test pair is robust. We prove that each of these problems is NP \Gamma complete. More importantly, we prove that the first two remain NP \Gamma complete for the simplest subcircuit design styles, namely series/parallel nMOS or CMOS logic gates. The third subproblem is shown to be of linear complexity for a CMOS logic gate with a stuck-open fault. We illustrate that a test pair that is not robust may contain a robust sub-test pair, and give a necessary and sufficient condition for this to happen in CMOS logic gates. This leads to a linear-time algorithm for CMOS logic gates which tests for robustness and, if possible, derives a robust test pair from a possibly non-robust pair. The implications of these complexity resu...

We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition t n and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the "conditional sum type" with delay t n (if it exists) together with a small complete test set with respect to the chosen fault model FM. Keywords---Circuit design, design for testability, area-time optimal adders, multidimensional dynamic programming. I. Introduction Since 1982, various VLSI designs for fast addition have been proposed [1], [2]. The delays of the adders presented are optimal from the asymptotic point of view. However, the actual optimal structure of a realistic adder depends on the cell library use...