Abstract — This paper describes a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input. The half-bridge is connected to a fully differential position-sense interface, the output of which is used for one-bit force feedback. By enclosing the proof mass in a one-bit feedback loop, simultaneous force balancing and analog-to-digital conversion are achieved. On-chip digital offset-trim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behavior. The fabricated singlechip accelerometer measures 4 2 4mm P, draws 27 mA from a 5-V supply, and has a dynamic range of 84, 81, and 70 dB along the �-, �-, and �-axes, respectively. Index Terms—Accelerometer, calibration, force balance, microelectromechanical systems (MEMS), sensor, sigma–delta.

OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog conve...

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. The reliability of these systems is aected by the ability of its constituent blocks to tolerate faults. Therefore, it is necessary to increase the reliability of ADCs to ensure a highly reliable critical system. This paper illustrates the steps involved in the reliability enhancement of ADCs by rst proposing a methodology for fault sensitivity analysis and then illustrating redesign techniques to improve the reliability of the highly sensitive(to faults) blocks. 1:

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. It is important to analyze the fault sensitivities of each of these to eectively gauge and improve the reliability of the system. This paper addresses the issue of fault sensitivity of ADCs. A generic methodology for analyzing the fault sensitivity of ADCs is presented. A novel concept of \node weights" speci c to -particle induced transient faults is introduced to increase the accuracy of such an analysis. 1. Introduction Fault sensitivity analysis allows the testing of the susceptibility of a circuit to dierent kinds of faults. This kind of study is necessary for space, military, avionics and biomedical applications. The purpose of such an analysis is to identify critical blocks in the circuit which are more susceptible to faults so that the...

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-m transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-m standard CMOS is 21 ps (48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-m standard CMOS process show successful sampling of every thirty-second bit of a 5-Gb/s data stream. Index Terms---Aperture time, CMOS integrated circuits, highspeed integrated circuits, sample and ...

This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 m heavily--doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme with the correlated double sampling (CDS) technique together, the virtually errorfree and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in the applications which require low-cost medium-speed and high-resolution A/D conversion. 1.

ii To my family whose encouragement and support have made this possible iii iv vi Microwave Doppler radar can be used for non-contact, through-clothing measurement of chest wall motion, from which heart and respiration signatures and rates can be derived in real-time. A heart and respiration rate monitor has been developed based on this princi-ple and the radio electronics have been integrated on a single CMOS chip, making inexpensive mass-production and miniaturization of the system possible. Although there are many potential applications for non-contact monitoring of heart and respiration rates, the fully integrated version focuses on the large and growing home monitoring market. This dissertation thoroughly explores the design requirements and trade-offs for this

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a digital unit to process it. Though considerable amount of research has been performed to increase the reliability of digital blocks, the same can not be claimed for mixed signal blocks. The reliability enhancement which we employ starts with fault sensitivity analysis followed by redesign. The data obtained from the sensitivity analysis is used to grade blocks based on their sensitivity to faults. The highly sensitive blocks can then be replaced by more reliable alternatives. The improvement gained by opting for more robust implementations might be limited due to the number of possible implementations. In these cases alternative reliability enhancement techniques such as adding redundancy may provide further improvements. The steps involved in the reliability enhancement of ADCs are illustrated in this paper by first proposing a sensitivity analysis methodology for #-particle induced transients and then suggesting redesign techniques to improve the reliability of the ADC. A novel concept of node weights specific to #-particle transients is introduced which improves the accuracy of the sensitivity analysis. The fault simulations show that, using techniques such as alternative robust implementations, adding redundancy, pattern detection and transistor sizing, considerable improvements in reliability can be attained.

Abstract — This paper presents analysis of a digital Ultrawideband (UWB) radio receiver operating in the 3.1 GHz to 10.6 GHz band. Analog to digital converter (ADC) bit precision is analyzed on two types of UWB signals- OFDM UWB and pulsed UWB- all in the presence of Additive White Gaussian Noise (AWGN) and a narrowband interferer in the channel. This paper shows how probability of error and the bit resolution of the ADC can be scaled depending on the Signal to Noise Ratio (SNR), Signal to Interference Ratio (SIR), and the type of UWB signal. It also includes considerations on timing recovery for pulsed UWB. I.