This paper discusses research challenges in developing methodologies and tools for the synthesis and analysis of a key component in portable digital communications and multimedia consumer electronics systems, namely, application-specific processors and associated compilers. For such applications it is typically desirable to implement functionality in software, however the penalty in cost/efficiency incurred by using general purpose processors , or even DSPs, may be unacceptable. Very Large Instruction Word (VLIW) Application Specific Instruction-Set Processors (ASIPs) realize cost/efficiency tradeoffs that can be very attractive for this market. However, difficulties with ASIP design and current compiler technology pose significant obstacles to this technology. In this paper we discuss these challenges and propose a framework to jointly address (1) the synthesis of VLIW ASIPs, and (2) the development of high-quality retargetable compilers for such specialized processors. Keyw...

Computer systems designed under the explicitly parallel instruction computing (EPIC) paradigm rely extensively on compiler technology to deliver the instruction-level parallelism (ILP) required for them to achieve high levels of performance. While manifold techniques have been proposed in the literature for delivering such parallelism, this dissertation is unique in integrating and applying a comprehensive suite of techniques, embodied in the IMPACT Research Compiler, to a concrete system, comprised of the SPEC CINT2000 benchmarks and the Intel Itanium 2 platform. These techniques include advanced pointer analysis, aggressive cross-file procedure inlining, targeted region formation, profile-guided optimizations, and, most importantly, aggressive and pervasive use of predication and control speculation. The collective effect of these techniques is evaluated with real-system measurements, showing them to achieve a 1.20 average (up to 1.59) speedup relative to classically optimized code and a 1.70 average (up to 2.51) speedup relative to code compiled with the Gnu GCC compiler. Achieving these results in the real-machine environment required advances in region formation heuristics, optimization, and speculation methods. Modern

family and friends for their continued support throughout this process. Most importantly, I would like to thank my ancee, Amy, for her boundless love and compassion. She has continued to encourage me in all my endeavors, despite our distance apart. This work could not have been completed without her devotion and understanding. iv TABLE OF CONTENTS Page 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. THE STARCORE SC140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 DALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 AGU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Hardware Looping . . . .

. The growing market of embedded systems and applications has led to the making of more general embedded processors, with some features traditionally associated with general-purpose microprocessors. Following this trend, recent research has tried to incorporate into embedded processors the newest techniques to break down ILP limits. Value speculation is a recent technique not yet considered in the context of embedded processors, and the goal of the present work is to analyse the performance potential of this technique within this scope. 1 Introduction Over the last few years, the increasing number of communication and multimedia applications has brought about a growing demand for high performance in embedded computing systems [1], [2], and many of the techniques for extracting InstructionLevel Parallelism (ILP), traditionally used in high performance general-purpose systems, are being applied to embedded processors [3]. The limits on the amount of extractable ILP are due to th...