This paper extends PVS's standard bitvector library with multiplication, division and remainder operations, together with associated results. This extension is needed to give appropriate semantics to Java's integral types in program verification. Special emphasis is therefore put on Java's widening and narrowing functions in relation to the newly defined operations on bitvectors.

AbstractÐErrors in computing systems can cause abnormal behavior and degrade data integrity and system availability. Errors should be avoided especially in embedded systems for critical applications. However, as the trend in VLSI technologies has been toward smaller feature sizes, lower supply voltages, and higher frequencies, there is a growing concern about temporary errors as well as permanent errors in embedded systems; thus, it is very essential to detect those errors. Software Implemented Hardware Fault Tolerance �SIHFT) is a low-cost alternative to hardware fault tolerance techniques for embedded processors: It does not require any hardware modification of Commercial Off-The-Shelf �COTS) processors. ED 4 I is a SIHFT technique that detects both permanent and temporary errors by executing two ªdifferentº programs �with the same functionality) and comparing their outputs. ED 4 I maps each number, x, in the original program into a new number x 0, and then transforms the program so that it operates on the new numbers so that the results can be mapped backwards for comparison with the results of the original program. The mapping in the transformation of ED 4 I is x 0 ˆ k x for integer numbers, where k determines the fault detection probability and data integrity of the system. For floating point numbers, we find a value of kf for the fraction and ke for the exponent separately and use k ˆ kf 2 ke for the value of k. We have demonstrated how to choose an optimal value of k for the transformation. This paper shows that, for integer programs, the transformation with k ˆ 2 was the most desirable choice in six out of seven benchmark programs we simulated. It maximizes fault detection probability under the condition that data integrity is highest. Index TermsÐSoftware implemented hardware fault tolerance �SIHFT), low cost fault tolerance, concurrent error detection, data diversity, duplicated instructions. 1

This paper presents Petri net software tool P3 that is developed for training purposes of the Architecture and organization of computers (AOC) course. The P3 has the following features: graphical modeling interface, interactive simulation by single and parallel (with previous conflict resolution) transition firing, two wellknown Petri net analysis tools (Reachability tree, Matrix equations), as well as two new analysis tools (Firing graph, and Firing graph) developed for learning purposes. The special aspect of the P3 is the XML/XSLT-based support for model sharing with the following Petri net tools: DaNAMiCS, Renew, and Petri Net Kernel (PNK). This paper also gives overview of the AOC course, and compares students’ outcomes in the AOC course when they used the P3, with the previous course outcome when the students did not use P3. Finally, the paper shows how teachers (i.e. we) and students perceived P3’s features.

Microcode is used to facilitate new technologies in Intel CPU designs. A critical

This thesis examines compile-time compaction of program execution traces. It presents a new method for compacting traces for memory simulation. Further, it describes a tool prototype that implements the method. Experiments with the tool prototype show that the new method reduces the time needed in simulating the operation of memories. Memory simulation is needed in the performance analysis and in the design of programs. In high performance applications, the data transfer between different layers of memory is one of the main bottlenecks. A program execution trace is a list of memory references. Using traces as simulation inputs is a flexible way of analyzing the memory perfor...

: The paper presents a Computer Architecture Learning and Knowledge Assessment System named the CALKAS. It is a software tool aimed to be used for teaching Computer architecture and organization. It offers the knowledge assessment and self-learning facilities. The knowledge assessment facilities are meant to be used in laboratory for the lab test and at home for the self-test. The self-learning facilities are meant to be used at home in the process of preparation for the work in the laboratory and for the exam. The CALKAS is developed as a WWW application. 1. Introduction At the Faculty of Electrical Engineering, University of Belgrade, there are a few undergraduate courses in the area of computer architecture and organization. The second year course in Computer architecture and organization attended by the students of all departments covers the basic concepts such as the processor architecture and organization, the memory, the input/output subsystem and the bus [1]. The third year c...

We present an investigation of the architecture of an optoelectronic cache which can integrate terabit optical memories with the electronic caches associated with high performance uni- and multi- processors. The use of optoelectronic cache memories will enable these terabit technologies to transparently provide low latency secondary memory with frame sizes comparable to disk-pages but with latencies approaching those of electronic secondary cache memories. This will enable the implementation of terabit memories with effective access times comparable to the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free space optical I/O to-and-from optical memory with conventional electronic communication to the processor caches. This cache, and the optical memory system to which it will interface, provides for a large random access memory space which has lower overall latency than that of magnetic disks and disk arrays. I...

We consider discretizations fN of expanding maps f : I ! I in the strict sense: i.e. we assume that the only information available on the map is a nite set of integers. Using this de nition for computability, we show that by adding a random perturbation of order 1=N , the invariant measure corresponding to f can be approximated and we can also give estimates of the error term. We prove that the randomized discrete scheme is equivalent to Ulam's scheme applied to the polygonal approximation of f , thus providing a new interpretation of Ulam's scheme. We also compare the eciency of the randomized iterative scheme to the direct solution of the N N linear system.

Computers are among the most exciting technical systems for younger students. Many students are keenly interested in learning how a modern computer works, but are unable to because of their limited background. We have developed a series of activities that mimic the operation of a digital computer to teach computer architecture concepts without the need for expensive equipment that are beyond the resources of most schools. Students role-play parts of a digital computer to accomplish a given task, and follow a given set of rules (their program). Student roles include: a processor, a cache memory controller, main memory, mass storage devices, system busses, and input/output devices. Student activities include displaying a multimedia movie, exploring cache memory, and processing an image. Preliminary testing indicates that the Classroom Computer allows students to understand the basic operations of a digital computer.

It is commonly held in current computer architecture literature that stack-based computers were entirely superseded by the combination of pipelined, integrated microprocessors and improved compilers. While correct, the literature omits a second, new generation of stack computers that emerged at the same time. In this thesis, I develop historical, qualitative, and quantitative distinctions between the first and second generations of stack computers. I present a rebuttal of the main arguments against stack computers and show that they are not applicable to those of the second generation. I also present an example of a small, modern stack computer and compare it to the MIPS architecture. The results show that second-generation stack computers have much better performance for deeply nested or recursive code, but are correspondingly worse for iterative code. The results also show that even though the stack computer’s zero-operand instruction format only moderately increases the code density, it significantly reduces instruction memory bandwidth.