The paper presents exact schedulability analyses for real-time systems scheduled at run-time with a static priority pre-emptive dispatcher. The tasks to be scheduled are allowed to experience internal blocking (from other tasks with which they share resources) and (with certain restrictions) release jitter — such as waiting for a message to arrive. The analysis presented is more general than that previously published, and subsumes, for example, techniques based on the Rate Monotonic approach. In addition to presenting the theory, an existing avionics case study is described and analysed. The predictions that follow from this analysis are seen to be in close agreement with the behaviour exhibited during simulation studies. 1.

Introduction Real-time systems and many other computer applications must meet specifications and perform tasks that satisfy timing as well as logical criteria for correctness. Examples of timing properties and constraints include deadlines, the periodic execution of processes, and external event recognition based on time of occurrence (e.g., [9, 18]). We present a scheme for reasoning with and about time and for specifying timing properties in concurrent programs. The objectives are to predict the tim1 This chapter is based on "Reasoning about Time in Higher-Level Language Software," by Alan Shaw that appeared in IEEE Transactions on Software Engineering, vol. 15, no. 7, pp. 875--889, July 1989, c fl1989 IEEE. Sec. 16.1 Introduction 375 ing behavior of higher-level language programs and to prove that they meet their timing constraints, through the direct analysis of program statements. Timing

Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a powerefficient version of a widely used fixed priority scheduling method. The method yields a power reduction by exploiting slack times, both those inherent in the system schedule and those arising from variations of execution times. The proposed run-time mechanism is simple enough to be implemented in most kernels. Experimental results show that the proposed scheduling method obtains a significant power reduction across several kinds of applications.

This paper surveys the design of embedded computer systems, which use software running on programmable computers to im-plement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design problewhe design of the hard-ware and software components influence each other. This paper emphasizes a historical approach to show the relationships be-tween well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hard-ware and sofhvare architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hard-ware-software co-design. We also describe design and synthesis techniques for co-design and related problems.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning...

1 Cache Memories and Real-Time Applications Caches are used to improve the access times of fast microprocessors to relatively slow main memories. They can reduce the number of cycles a processor is waiting for data by providing faster access to recently referenced regions of memory1. Programs with hard real time constraints have to be subjected to a schedulability analysis by the compiler [17, 6]; it has to be determined whether all timing constraints can be satisfied. WCETs (Worst Case Execution Times) for processes have to be used for this. For hardware with caches, the appropriate worst case assumption is that all accesses miss the cache. This is an overly pessimistic assumption which leads to a waste of hardware resources. 1 Hennessy and Patterson [8] describe typical values for caches in 1990 workstations

. A number of methods have been presented to calculate the worst case execution time (WCET) of real-time programs. However, to properly handle semantic dependencies, which in most cases is needed to reduce overestimation, all these methods require extra semantic information to be given by the programmer (manual annotations for paths, loops and recursion depth). To manually derive these annotations is often difficult and the process is error-prone. In this paper we present a new method to automatically derive safe and tight annotations for paths and loops. We illustrate our method by giving some examples and by presenting a prototype tool, implementing the method for a subset of C. 1 Introduction Real-time systems are systems in which the correctness depends not only on the results of computations, but also on the time at which the result is produced. To be able to guarantee the deadlines of a real-time system, the software execution time is needed before run-time. The execution time o...

The use of embedded programmable units in everydaylife is constantly increasing. An obvious example for this are modern cars. Wiring harnesses are replaced by bus sys-tems, switches by smart switches and engine controllers by powerful CPUs. This allows for easy integration of addi\Lambda The work presented in this paper is supported by the European Union under Grant Next TTA "IST-2001-32111 " and the French Department ofDefence.

. The knowledge of program execution times is crucial for the development and the verification of real-time software. Therefore, there is a need for methods and tools to predict the timing behavior of pieces of program code and entire programs. This paper presents a novel method for the analysis of program execution times. The computation of MAximum eXecution Times (MAXTs) is mapped onto a graph-theoretical problem that is a generalization of the computation of a maximum cost circulation in a directed graph. Programs are represented by T-graphs, timing graphs, which are similar to flow graphs. These graphs reflect the structure and the timing behavior of the code. Relative capacity constraints, a generalization of capacity constraints that bound the flow in the edges, express user-supplied information about infeasible paths. To compute MAXTs, T-graphs are searched for those execution paths which correspond to a maximum cost circulation. The search problem is transformed into an integer...

Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. This paper describes three complementary methods to support timing analysis by bounding the number of loop iterations. First, an algorithm is presented that determines the minimum and maximum number of iterations of loops with multiple exits. Second, the loopinvariant variables on which the number of loop iterations depends are identified for which the user can provide minimum and maximum values. Finally, a method is given to tightly predict the execution time of loops whose number of iterations is dependent on counter variables of outer level loops. These methods have been successfully integrated in an existing timing analyzer that predicts the performance for optimized code on a machine that exploits caching and pipelining. The result is tighter timing analysis predictions and less work for the user.