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23
Complexity and Algorithms for Reasoning About Time: A GraphTheoretic Approach
, 1992
"... Temporal events are regarded here as intervals on a time line. This paper deals with problems in reasoning about such intervals when the precise topological relationship between them is unknown or only partially specified. This work unifies notions of interval algebras in artificial intelligence ..."
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Cited by 86 (11 self)
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Temporal events are regarded here as intervals on a time line. This paper deals with problems in reasoning about such intervals when the precise topological relationship between them is unknown or only partially specified. This work unifies notions of interval algebras in artificial intelligence with those of interval orders and interval graphs in combinatorics. The satisfiability, minimal labeling, all solutions and all realizations problems are considered for temporal (interval) data. Several versions are investigated by restricting the possible interval relationships yielding different complexity results. We show that even when the temporal data comprises of subsets of relations based on intersection and precedence only, the satisfiability question is NPcomplete. On the positive side, we give efficient algorithms for several restrictions of the problem. In the process, the interval graph sandwich problem is introduced, and is shown to be NPcomplete. This problem is als...
Optimizing TwoPhase, LevelClocked Circuitry (Extended Abstract)
"... We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster ..."
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Cited by 55 (16 self)
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We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster levelclocked one. We model a twophase circuit as a graph whose vertex set V is a collection of combinational logic blocks, and whose edge set E is a set of interconnections. Each interconnection passes through 0 or more latches, where each latch is clocked by one of two periodic, nonoverlapping waveforms, or phases. We give efficient polynomialtime algorithms for problems involving the timing verification and optimization of twophase circuitry. Included are algorithms for ffl verifyi...
Reasoning About Temporal Relations: The Tractable Subalgebras Of Allen's Interval Algebra
 Journal of the ACM
, 2001
"... Allen's interval algebra is one of the best established formalisms for temporal reasoning. This paper is the final step in the classification of complexity in Allen's algebra. We show that the current knowledge about tractability in the interval algebra is complete, that is, this algebra contains ex ..."
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Cited by 30 (2 self)
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Allen's interval algebra is one of the best established formalisms for temporal reasoning. This paper is the final step in the classification of complexity in Allen's algebra. We show that the current knowledge about tractability in the interval algebra is complete, that is, this algebra contains exactly eighteen maximal tractable subalgebras, and reasoning in any fragment not entirely contained in one of these subalgebras is NPcomplete. We obtain this result by giving a new uniform description of the known maximal tractable subalgebras and then systematically using an algebraic technique for identifying maximal subalgebras with a given property.
DribbleBack Registers: A Technique For Latency Tolerance In Multiprocessors
, 1992
"... As parallel machines grow in scale and complexity, latency tolerance of synchroniza tion faults and remote memory accesses becomes increasingly important. One method for tolerating this latency is by multithreading the processor and rapidly context switching between these threads. Fast context swit ..."
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Cited by 9 (0 self)
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As parallel machines grow in scale and complexity, latency tolerance of synchroniza tion faults and remote memory accesses becomes increasingly important. One method for tolerating this latency is by multithreading the processor and rapidly context switching between these threads. Fast context switching is most effective when the latencies being tolerated are short compared to the total run lengths of all the resident threads. If this condition is not met, it may become necessary to expend processor cycles to unload a blocked thread and load in a new one. This thesis presents the dribblein, dribbleout register file, which facilitates fast context switching and the ability to hide the latency of loading and unloading context state. Through an analytical model and a simulation framework, we show that the dribblein, dribbleout register file compares favorably against existing designs.
A Timing Analysis and Optimization System for LevelClocked Circuitry
, 1993
"... This thesis investigates timing analysis and optimization issues in synchronous circuitry. The major thrust of our work is a collection of provably correct and efficient algorithms that perform a variety of architecturallevel operations on levelclocked circuitry, that is, circuitry that employs a ..."
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Cited by 7 (5 self)
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This thesis investigates timing analysis and optimization issues in synchronous circuitry. The major thrust of our work is a collection of provably correct and efficient algorithms that perform a variety of architecturallevel operations on levelclocked circuitry, that is, circuitry that employs a multiphase clocking scheme and levelclocked storage elements. We implemented several of these algorithms in Tim, a timing package for twophase, levelclocked circuitry. Using Tim we empirically compared the performance and the storage element requirements of edgetriggered and equivalent levelclocked implementations of synchronous circuitry. Our research contributes towards a better understanding of the complex timing issues involved in levelclocking and provides the enabling technology for bringing levelclocking into the mainstream of circuit design. We begin by describing algorithms for optimizing edgetriggered circuitry in Chapter 1. This kind of circuitry is particularly popular a...
Satisfiability Problems on Intervals and Unit Intervals
 Theoretical Computer Science
, 1997
"... For an interval graph with some additional order constraints between pairs of nonintersecting intervals, we give a linear time algorithm to determine if there exists a realization which respects the order constraints. Previous algorithms for this problem (known also as seriation with side constrain ..."
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Cited by 5 (1 self)
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For an interval graph with some additional order constraints between pairs of nonintersecting intervals, we give a linear time algorithm to determine if there exists a realization which respects the order constraints. Previous algorithms for this problem (known also as seriation with side constraints) required quadratic time. This problem contains as subproblems interval graph and interval order recognition. On the other hand, it is a special case of the interval satisfiability problem, which is concerned with the realizability of a set of intervals along a line, subject to precedence and intersection constraints. We study such problems for all possible restrictions on the types of constraints, when all intervals must have the same length. We give efficient algorithms for several restrictions of the problem, and show the NPcompleteness of another restriction. 1 Introduction Two intervals x; y on the real line may either intersect or one of them is completely to the left of the othe...
An Integrated, BreadthFirst Computer Science Curriculum Based on Computing Curricula 1991
 In TwentyFourth SIGCSE Technical Symposium on Computer Science Education (SIGCSE Bulletin
, 1993
"... this paper makes a detailed discussion of the new curriculum impossible. A more complete description can be obtained from the authors [Paxton, Ross, and Starkey 19931]. ..."
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Cited by 5 (2 self)
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this paper makes a detailed discussion of the new curriculum impossible. A more complete description can be obtained from the authors [Paxton, Ross, and Starkey 19931].
RunTime Thread Management for LargeScale DistributedMemory Multiprocessors
, 1993
"... Effective thread management is crucial to achieving good performance on largescale distributedmemory multiprocessors that support dynamic threads. For a given parallel computation with some associated task graph, a threadmanagement algorithm produces a running schedule as output, subject to the p ..."
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Cited by 3 (0 self)
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Effective thread management is crucial to achieving good performance on largescale distributedmemory multiprocessors that support dynamic threads. For a given parallel computation with some associated task graph, a threadmanagement algorithm produces a running schedule as output, subject to the precedence constraints imposed by the task graph and the constraints imposed by the interprocessor communications network. Optimal thread management is an NPhard problem, even given full a priori knowledge of the entire task graph and assuming a highly simplified architecture abstraction. Thread management is even more difficult for dynamic datadependent computations which must use online algorithms because their task graphs are not known a priori. This thesis investigates online threadmanagement algorithms and presents XTM, an online threadmanagement system for largescale distributedmemory multiprocessors. XTM has been implemented for the MIT Alewife Multiprocessor. Simulation results...
Software Based Instruction Caching for the RAW Architecture
, 1999
"... This thesis addresses the design and implementation of a software based instruction caching system for the RAW architecture. This system is necessary to allow large programs to be run in the limited onchip memory available for each RAW tile. Similar systems were examined and various design issues w ..."
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Cited by 3 (1 self)
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This thesis addresses the design and implementation of a software based instruction caching system for the RAW architecture. This system is necessary to allow large programs to be run in the limited onchip memory available for each RAW tile. Similar systems were examined and various design issues were examined in detail. A partial system was implemented in the RAW compiler in order to gauge the feasibility of such a system. Performance data was collected from various benchmarks. The implications of this data and directions for further research are discussed.