Results 1  10
of
15
PerformanceDriven Interconnect Design Based on Distributed RC Delay Model
 in Proc. Design Automation Conf
, 1993
"... In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimizat ..."
Abstract

Cited by 69 (21 self)
 Add to MetaCart
(Show Context)
In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or nearoptimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for highperformance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, ...
Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization
, 1996
"... This paper presents an e cient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that t ..."
Abstract

Cited by 64 (16 self)
 Add to MetaCart
This paper presents an e cient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performancedriven Atree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach.
Optimal Wiresizing Under the Distributed Elmore Delay Model
 in Proc. Int. Conf. on Computer Aided Design
, 1993
"... In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we deve ..."
Abstract

Cited by 58 (26 self)
 Add to MetaCart
(Show Context)
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomialtime optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 51% when compared to the uniformwidth solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in [7], our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timingcritical sinks by up to 12%. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnection delay has...
NearOptimal Critical Sink Routing Tree Constructions
, 1995
"... We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at id ..."
Abstract

Cited by 55 (13 self)
 Add to MetaCart
(Show Context)
We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67%) over minimum Steiner routings in terms of delays to identified critical sinks. ERTs also serve as generic highperformance routing trees when no critical sink is specified: for 8sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the mini...
HighPerformance Routing Trees With Identified Critical Sinks
, 1992
"... We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significa ..."
Abstract

Cited by 38 (13 self)
 Add to MetaCart
(Show Context)
We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower criticalsink delays compared with existing performancedriven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69 % over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.
Coping with RC(L) Interconnect Design Headaches
 in Proc. of the International Conference on ComputerAided Design
, 1995
"... Physical interconnect effects have a dominant impact on today’s deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre and po ..."
Abstract

Cited by 22 (0 self)
 Add to MetaCart
(Show Context)
Physical interconnect effects have a dominant impact on today’s deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre and postlayout interconnect design.This coverage will not be an exhaustive summary, but one that is primarily focused on momentbased analysis techniques, from the Elmore delay, to the more recent advances in momentmatching approximations, and the corresponding nonlinear driver/load interfaces. Future modeling, analysis, and design challenges will be considered throughout this paper. 1
Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion
 In Proc. ACM/SIGDA Physical Design Workshop
, 1996
"... This paper presents an algorithm for interconnect layout optimization with buffer insertion. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a buffered Steiner tree so that the required arrival time (or timi ..."
Abstract

Cited by 21 (4 self)
 Add to MetaCart
(Show Context)
This paper presents an algorithm for interconnect layout optimization with buffer insertion. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a buffered Steiner tree so that the required arrival time (or timing slack) at the source is maximized. In the algorithm, Steiner routing tree construction and buffer insertion are achieved simultaneously by combining Atree construction and dynamic programming based buffer insertion algorithms, while these two steps were carried out independently in the past. Extensive experimental results indicate that our approach outperforms conventional twostep approaches. Our buffered Steiner trees increase the timing slack at the source by up to 75% compared with those by the conventional approaches. 1. Introduction For timing optimization of VLSI circuits, buffer insertion (or fanout optimization) and interconnect topology optimization take important roles and a ...
Delay Minimization for ZeroSkew Routing
 Proc. IEEE Intl. Conf. ComputerAided Design
, 1993
"... Delay minimization methods are proposed for zeroskew routings. A delaytime estimation formula is derived, which can be used as an objective function to be minimized in zeroskew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a cl ..."
Abstract

Cited by 20 (1 self)
 Add to MetaCart
(Show Context)
Delay minimization methods are proposed for zeroskew routings. A delaytime estimation formula is derived, which can be used as an objective function to be minimized in zeroskew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a clusteringbased algorithm achieve 50% reduction of the delay time on benchmark data with 3000 pins. 1 Department of Computer Science, Princeton University and C&C Systems Research Laboratories, NEC Corporation 1 Introduction With the increase of the clock rate in VLSI, the clocknet routing scheme plays more critical roles. In order to make the clock rate higher, at least two factors should be taken into account in clocknet routing. First, since the clock skew affects the clock period directly, exact zero skew is desired. Next, the delay time should be minimized in a clock net. Consider an example of singlephase clocking in Fig. 1. In CMOS design, the delay time is dominated by the rise/f...
A simplified synthesis of transmission lines with a tree structure
 Journal of Analog Integrated Circuits and Signal Processing (Special Issue on HighSpeed Interconnects
, 1994
"... Abstract. The limiting factor for highperformance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chiptochip interconnection on mul ..."
Abstract

Cited by 18 (5 self)
 Add to MetaCart
Abstract. The limiting factor for highperformance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chiptochip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributed RLC tree which models interconnections in highspeed IC chips. The presented result can be used to calculate the waveform and delay in an RLC tree. The result on the RLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a twopole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout. 1.
Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments
 Proc. European Design Automation Conf
, 1994
"... In performancedriven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of momentmatching, or moment representation, methods used to simulate interconnects modeled as distributed RC or RLC lines. We provide acc ..."
Abstract

Cited by 13 (2 self)
 Add to MetaCart
(Show Context)
In performancedriven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of momentmatching, or moment representation, methods used to simulate interconnects modeled as distributed RC or RLC lines. We provide accurate 2 and 3segment equivalent circuits for the distributed RLC and distributed RC models. Our equivalent circuits approximate a distributed RLC structure accurately up to second degree terms. We have evaluated our models using the twopole methodology for voltage response calculations. Previous approximate twopole approaches have at least 14% error even for small test cases. As routing trees become bigger and interconnection lines become longer, our approach has greater advantages in both accuracy and simulation complexity. 1 Overview Accurate calculation of propagation delay in VLSI interconnects is critical to the design of high speed systems. Direct simulation codes such as SPICE ...