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Abstraction Mechanisms for Hardware Verification
 VLSI Specification, Verification and Synthesis
, 1987
"... ion Mechanisms for Hardware Verification Thomas F. Melham University of Cambridge Computer Laboratory New Museums Site, Pembroke Street Cambridge, CB2 3QG, England Abstract: It is argued that techniques for proving the correctness of hardware designs must use abstraction mechanisms for relating fo ..."
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ion Mechanisms for Hardware Verification Thomas F. Melham University of Cambridge Computer Laboratory New Museums Site, Pembroke Street Cambridge, CB2 3QG, England Abstract: It is argued that techniques for proving the correctness of hardware designs must use abstraction mechanisms for relating formal descriptions at different levels of detail. Four such abstraction mechanisms and their formalization in higher order logic are discussed. Introduction Recent advances in microelectronics have given designers of digital hardware the potential to build electronic devices of unprecedented size and complexity. With increasing size and complexity, however, it becomes increasingly difficult to ensure that such systems will not malfunction because of design errors. This problem has prompted some researchers to look for a firm theoretical basis for correct design of hardware systems. Mathematical methods have been developed to model the functional behaviour of electronic devices and to verify,...
Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
A Practical Methodology for the Formal Verification of RISC Processors
, 1995
"... In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage leve ..."
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In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage level, the clock phase level and the hardware implementation. The use of this model allows us to successively prove the correctness between two neighbouring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into two independent steps. The first step shows that each architectural instruction is implemented correctly by the sequential execution of its pipeline stages. The second step shows that the instructions are correctly processed by the pipeline in that we prove that under certain constraints from the actual architecture, no conflic...
COMPARING HOL AND MDG: A CASE STUDY ON THE VERIFICATION OF AN ATM SWITCH FABRIC
 NORDIC JOURNAL OF COMPUTING
, 1998
"... Interactive formal proof and automated verification based on decision graphs are two contrasting formal hardware verification techniques. In this paper, we compare these two approaches. In particular, we consider HOL and MDG. The former is an interactive theoremproving system based on higherorder ..."
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Cited by 3 (2 self)
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Interactive formal proof and automated verification based on decision graphs are two contrasting formal hardware verification techniques. In this paper, we compare these two approaches. In particular, we consider HOL and MDG. The former is an interactive theoremproving system based on higherorder logic, while the latter is an automatic system based on Multiway Decision Graphs. As the basis for our comparison we have used both systems to independently verify a fabricated ATM communications chip, the Fairisle 4 by 4 switch fabric.
Stronglytyped Theory of Structures And Behaviours
 Correct Hardware Design and Verification Methods, Lecture Notes In Computer Science
, 1993
"... This paper describes an approach to capturing the relation between circuits and their behaviours within a formal theory. The method exploits dependent types to achieve a rigorous yet theoretically simple connection between circuits (treated as graphs) and their behavioural specifications (treate ..."
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This paper describes an approach to capturing the relation between circuits and their behaviours within a formal theory. The method exploits dependent types to achieve a rigorous yet theoretically simple connection between circuits (treated as graphs) and their behavioural specifications (treated as predicates). An example is given of a behavioural extraction function and it is shown how a type for modules can be defined that is sufficiently fine to guarantee that the behaviour of a module will satisfy its behavioural specification. The method is discussed in relation to VHDL and in relation to formal synthesis, (a process whereby one starts with a behavioural specification and, using an interactive goaldirected approach, ends up with a circuit and a formal proof that it satisfies the given behavioural specification).
Nuprl and its Use in Circuit Design
, 1992
"... Nuprl is an interactive theorem proving system in the LCF tradition. It has a higher order logic and a very expressive type theory; the type theory includes dependent function types (\Pi types), dependent product types (\Sigma types) and set types. Nuprl also has a well developed XWindows user inte ..."
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Nuprl is an interactive theorem proving system in the LCF tradition. It has a higher order logic and a very expressive type theory; the type theory includes dependent function types (\Pi types), dependent product types (\Sigma types) and set types. Nuprl also has a well developed XWindows user interface and allows for the use of clear and concise notations, close to ones used in print. Proofs are objects which can be viewed, and serve as readable explanations of theorems. Tactics provide a highlevel extendible toolkit for proof development, while the soundness of the system relies only a fixed set of rules. We give an overview of the Nuprl system, focusing in particular on the advantages that the type theory brings to formal methods for circuit design. We also discuss ongoing projects in verifying floatingpoint circuits, verifying the correctness of hardware synthesis systems, and synthesizing circuits by exploiting the constructivity of Nuprl's logic. Keyword Codes: F.4.1; B.6.2; I...
A Formalization of a Hierarchical Model for RISC Processors
, 1993
"... . Since microprocessors are used in many areas of realtime control, the use of formal methods provides an alternative approach for achieving high reliability. In this paper, a methodology based on a hierarchical model of interpreters is presented for formalizing RISCs in general. The abstraction le ..."
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. Since microprocessors are used in many areas of realtime control, the use of formal methods provides an alternative approach for achieving high reliability. In this paper, a methodology based on a hierarchical model of interpreters is presented for formalizing RISCs in general. The abstraction levels used by a designer in the implementation of RISCs, namely the instruction set level, the pipeline stage level, the phase level and the hardware implementation, are mirrored by this hierarchical model. Hence the informal specifications given by the user, at each level of abstraction, can be easily converted into a formal specification, in higher order logic. Such a model is of great use in formal verification and also synthesis using transformational reasoning. 1 Introduction As computer systems are becoming increasingly complex, the trustworthiness of their design is questionable. Conventional approaches such as simulation and testing have a very high cost to confidencegain ratio and ...
Comparing HOL, MDG and VIS: A Case Study on the Verification of an ATM Switch Fabric
, 1999
"... There exist a wide range of hardware verification tools, some based on interactive theorem proving and other more automated tools based on decision diagrams. In this paper, we compare three different verification systems covering the spectrum of today's verification technology. In particular, we con ..."
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There exist a wide range of hardware verification tools, some based on interactive theorem proving and other more automated tools based on decision diagrams. In this paper, we compare three different verification systems covering the spectrum of today's verification technology. In particular, we consider HOL, MDG and VIS. HOL is an interactive theorem proving system based on higherorder logic. VIS is an automatic system based on ROBDDs and integrating verification with simulation and synthesis. The MDG system is an intermediate approach based on Multiway Decision Graphs providing automation while accommodating abstract data sorts, uninterpreted functions and rewriting. As the basis for our comparison we used all three systems to independently model and verify a fabricated ATM communications chip: the Fairisle 4 4 switch fabric.
Eliminating HigherOrder Quantifiers to Obtain Decision Procedures for Hardware Verification
"... . In this paper, we present methods for eliminating higherorder quantifiers in proof goals arising in the verification of digital circuits. For the description of the circuits, a subset of higherorder logic called hardware formulae is used which is sufficient for describing hardware specifications ..."
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. In this paper, we present methods for eliminating higherorder quantifiers in proof goals arising in the verification of digital circuits. For the description of the circuits, a subset of higherorder logic called hardware formulae is used which is sufficient for describing hardware specifications and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Verification goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higherorder logic, e.g. (temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90. 1 Introduction Higherorder logic is well suited for hardware verification [Gord86, Joyc91], but unfortunately this logic is neither ...
A Synchronous VHDL Subset with a Formal Semantics in HOL
"... VHDL is frequently used for describing purely synchronous circuits. However, the underlying model of VHDL is much more expressive than it need be. In this report, a synchronous subset of VHDL named ABCVHDL is introduced. ABCVHDL is dedicated towards logical argumentation and correct circuit synthe ..."
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VHDL is frequently used for describing purely synchronous circuits. However, the underlying model of VHDL is much more expressive than it need be. In this report, a synchronous subset of VHDL named ABCVHDL is introduced. ABCVHDL is dedicated towards logical argumentation and correct circuit synthesis based on VHDL descriptions. Although being conform with the standard VHDL semantics, the semantics of ABCVHDL is based on a far simpler model: synchronous circuit descriptions at the RTlevel formalized within higher order logic. This article describes the syntactical aspects of ABCVHDL, and it also defines the semantics of ABCVHDL by a mapping between ABCVHDL structures and the corresponding formulae in higher order logic.