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133
DivideandConquer Approximation Algorithms via Spreading Metrics
, 1996
"... We present a novel divideandconquer paradigm for approximating NPhard graph optimization problems. The paradigm models graph optimization problems that satisfy two properties: First, a divideandconquer approach is applicable. Second, a fractional spreading metric is computable in polynomial tim ..."
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Cited by 98 (10 self)
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We present a novel divideandconquer paradigm for approximating NPhard graph optimization problems. The paradigm models graph optimization problems that satisfy two properties: First, a divideandconquer approach is applicable. Second, a fractional spreading metric is computable in polynomial time. The spreading metric assigns rational lengths to either edges or vertices of the input graph, such that all subgraphs on which the optimization problem is nontrivial have large diameters. In addition, the spreading metric provides a lower bound, ø , on the cost of solving the optimization problem. We present a polynomial time approximation algorithm for problems modeled by our paradigm whose approximation factor is O (minflog ø log log ø; log k log log kg), where k denotes the number of "interesting" vertices in the problem instance, and is at most the number of vertices. We present seven problems that can be formulated to fit the paradigm. For all these problems our algorithm improves ...
Special Purpose Parallel Computing
 Lectures on Parallel Computation
, 1993
"... A vast amount of work has been done in recent years on the design, analysis, implementation and verification of special purpose parallel computing systems. This paper presents a survey of various aspects of this work. A long, but by no means complete, bibliography is given. 1. Introduction Turing ..."
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Cited by 77 (5 self)
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A vast amount of work has been done in recent years on the design, analysis, implementation and verification of special purpose parallel computing systems. This paper presents a survey of various aspects of this work. A long, but by no means complete, bibliography is given. 1. Introduction Turing [365] demonstrated that, in principle, a single general purpose sequential machine could be designed which would be capable of efficiently performing any computation which could be performed by a special purpose sequential machine. The importance of this universality result for subsequent practical developments in computing cannot be overstated. It showed that, for a given computational problem, the additional efficiency advantages which could be gained by designing a special purpose sequential machine for that problem would not be great. Around 1944, von Neumann produced a proposal [66, 389] for a general purpose storedprogram sequential computer which captured the fundamental principles of...
Online admission control and circuit routing for high performance computing and communication
, 1994
"... This paper considers the problems of admission control and virtual circuit routing in high performance computing and communication systems. Admission control and virtual circuit routing problems arise in numerous applications, including videoservers, realtime database servers, and the provision of ..."
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Cited by 69 (7 self)
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This paper considers the problems of admission control and virtual circuit routing in high performance computing and communication systems. Admission control and virtual circuit routing problems arise in numerous applications, including videoservers, realtime database servers, and the provision of permanent virtual channels in largescale communications networks. The paper describes both upper and lower bounds on the competitive ratio of algorithms for admission control and virtual circuit routing in trees, arrays, and hypercubes (the networks most commonly used in conjunction with high performance computing and communication). Our results include optimal algorithms for admission control and virtual circuit routing in trees, as well as the first competitive algorithms for these problems on nontree networks. A key result of our research is the development of online algorithms that substantially outperform the greedybased approaches that are used in practice.
Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization)
 In Proceedings of the International Symposium on Field Programmable Gate Arrays
, 1999
"... FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with effic ..."
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Cited by 58 (7 self)
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FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 8090%), we can achieve more area efficient designs by allowing some LUTs to go unusedallowing us to use the dominant resource, interconnect, more efficiently. This extends the "Seaofgates " philosophy, familiar to mask programmable gate arrays, to FPGAs. Also introduced in this work is an algorithm for "depopulating " the gates in a hierarchical network to match the limited wiring resources. 1 Introduction The ability of an FPGA to support designs with high LUT usage is regularly touted as a feature. However, high routability across a variety of designs comes at a large expense in ...
Planar Separators and Parallel Polygon Triangulation
"... We show how to construct an O ( p n)separator decomposition of a planar graph G in O(n) time. Such a decomposition defines a binary tree where each node corresponds to a subgraph of G and stores an O ( p n)separator of that subgraph. We also show how to construct an O(n)way decomposition tree in ..."
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Cited by 53 (8 self)
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We show how to construct an O ( p n)separator decomposition of a planar graph G in O(n) time. Such a decomposition defines a binary tree where each node corresponds to a subgraph of G and stores an O ( p n)separator of that subgraph. We also show how to construct an O(n)way decomposition tree in parallel in O(log n) time so that each node corresponds to a subgraph of G and stores an O(n 1=2+)separator of that subgraph. We demonstrate the utility of such a separator decomposition by showing how it can be used in the design of a parallel algorithm for triangulating a simple polygon deterministically in O(log n) time using O(n = log n) processors on a CRCW PRAM.
Embedding graphs in books: a layout problem with applications to VLSI design
 SIAM J. ALGEBRAIC DISCRETE METHODS
, 1987
"... We study the graphtheoretic problem of embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross. This problem abstracts layout problems arising in the routing of multilayer printed ..."
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Cited by 49 (0 self)
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We study the graphtheoretic problem of embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross. This problem abstracts layout problems arising in the routing of multilayer printed circuit boards and in the design of faulttolerant processor arrays. In devising an embedding, one strives to minimize both the number of pages used and the "cutwidth" of the edges on each page. Our main results (1) present optimal embeddings of a variety of families of graphs; (2) exhibit situations where one can achieve small pagenumber only at the expense of large cutwidth; and (3) establish bounds on the minimum pagenumber of a graph based on various structural properties of the graph. Notable in the last category are proofs that (a) every nvertex dvalent graph can be embedded using O(dn1/2) pages, and (b) for every d>2 and all large n, there are nvertex dvalent graphs whose pagenumber is at least log n]&quot;
Which crossing number is it, anyway
 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
, 1998
"... A drawing of a graph G is a mapping which assigns to each vertex a point of the plane and to each edge a simple continuous arc connecting the corresponding two points. The crossing number of G is the minimum number of crossing points in any drawing of G. We define two new parameters, as follows. The ..."
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Cited by 42 (8 self)
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A drawing of a graph G is a mapping which assigns to each vertex a point of the plane and to each edge a simple continuous arc connecting the corresponding two points. The crossing number of G is the minimum number of crossing points in any drawing of G. We define two new parameters, as follows. The pairwise crossing number (resp. the oddcrossing number) of G is the minimum number of pairs of edges that cross (resp. cross an odd number of times) over all drawings of G. We prove that the largest of these numbers (the crossing number) cannot exceed twice the square of the smallest (the oddcrossing number). Our proof is based on the following generalization of an old result of Hanani, which is of independent interest. Let G be a graph and let E0 be a subset of its edges such that there is a drawing of G, in which every edge belonging to E0 crosses any other edge an even number of times. Then G can be redrawn so that the elements of E0 are not involved in any crossing. Finally, we show that the determination of each of these parameters is an NPhard problem and it is NPcomplete in the case of the crossing number and the oddcrossing number. 1
Horizons of Parallel Computation
 JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
, 1993
"... This paper considers the ultimate impact of fundamental physical limitationsnotably, speed of light and device sizeon parallel computing machines. Although we fully expect an innovative and very gradual evolution to the limiting situation, we take here the provocative view of exploring the ..."
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Cited by 39 (3 self)
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This paper considers the ultimate impact of fundamental physical limitationsnotably, speed of light and device sizeon parallel computing machines. Although we fully expect an innovative and very gradual evolution to the limiting situation, we take here the provocative view of exploring the consequences of the accomplished attainment of the physical bounds. The main result is that scalability holds only for neighborly interconnections, such as the square mesh, of boundedsize synchronous modules, presumably of the areauniversal type. We also discuss the ultimate infeasibility of latencyhiding, the violation of intuitive maximal speedups, and the emerging novel processortime tradeoffs.