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Boolean analysis of MOS circuits
 IEEE Transactions on Computeraided Design
, 1987
"... The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically ..."
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Cited by 70 (14 self)
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The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switchlevel simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, passtransistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.
Algorithmic Aspects of Symbolic Switch Network Analysis
 IEEE Trans. CAD/IC
, 1987
"... A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean eq ..."
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Cited by 22 (5 self)
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A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metaloxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.
Symbolic Verification of MOS Circuits
, 1985
"... The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and pr ..."
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Cited by 13 (6 self)
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The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and present input variables. By using heuristically efficient Boolean function manipulation algorithms, the verification of a circuit by symbolic simulation can proceed much more quickly than by exhaustive logic simulation. In this paper we present our concept of symbolic simulation, derive an algorithm for switchlevel symbolic simulation, and present experimental measurements from MOSSYM.
Verification of SwitchLevel Designs with ManyValued Logic
, 1993
"... This paper is an approach to automated verification of circuits represented as switch level designs. Switch level models (SLM) are a well established framework for modelling low level properties of circuits. We use many valued propositional logic to represent a suitable variant of SLM. Logical prope ..."
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Cited by 10 (4 self)
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This paper is an approach to automated verification of circuits represented as switch level designs. Switch level models (SLM) are a well established framework for modelling low level properties of circuits. We use many valued propositional logic to represent a suitable variant of SLM. Logical properties of circuits (gate level) can be expressed in a standard way in the same logic. As a result we can express soundness of switch level designs wrt to gate level specifications as many valued deduction problems. Recent advances in many valued theorem proving indicate that it is possible to handle real life examples. We report first results obtained with an experimental theorem prover.
Combinational static CMOS networks
, 1987
"... We develop mathematical switchlevel models for static combinational CMOS networks. In contrast to other dVdihbk MOS models and theories, our models capture design principles that are special to CMOS, such as the use of transmission gates. First we study networks consisting of cascade connections ..."
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Cited by 2 (1 self)
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We develop mathematical switchlevel models for static combinational CMOS networks. In contrast to other dVdihbk MOS models and theories, our models capture design principles that are special to CMOS, such as the use of transmission gates. First we study networks consisting of cascade connections of CMOS cells realizing negative functions. We then extend this model to incorporate transmission gates. Finally, we develop a more complex CMOS graph model which includes a ternary transient analysis and is capable of handling some unconventional, but commercially used, combinational networks. Such designs cannot be properly explained by presently available theories. Also, we discuss several general design approaches.
AFL1: A Programming Language for . . .
, 1986
"... Computational models are arising in which programs are constructed by specifying large networks of very simple computational devices. Although such models can potentially make use of a massive amount of concurrency, their usefulness as a programming model for the design of complex systems will ultim ..."
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Computational models are arising in which programs are constructed by specifying large networks of very simple computational devices. Although such models can potentially make use of a massive amount of concurrency, their usefulness as a programming model for the design of complex systems will ultimately be decided by the ease in which such networks can be programmed (constructed). This thesis outlines a language for specifying computational networks. The language (AFL1) consists of a set of primitives, and a mechanism to group these elements into higher level structures. An implementation of this language runs on the Thinking Machines Corporation, Connection Machine. Two significant examples were programmed in the language, an expert system (CIS), and a planning system (AFPLAN). These systems are explained and analyzed in terms of how they compare with similar systems written in conventional languages.
Computing Reviews Classification: B.5.2
"... ein. Hierbei wird das gewünschte Verhalten der Schaltung ..."
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Reasoning About The VHDL Standard Logic Package Signal Data Type
"... Formal verification methods provide a way to prove that a circuit structure correctly implements its specification. Low level gate and transistor logic circuits can be verified using methods such as symbolic simulation. Higher level circuits can be verified using theoremproving methods, providing ..."
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Formal verification methods provide a way to prove that a circuit structure correctly implements its specification. Low level gate and transistor logic circuits can be verified using methods such as symbolic simulation. Higher level circuits can be verified using theoremproving methods, providing a multileveled approach to complex device verification. Correct modeling of many VLSI circuits requires a signal value data type that includes some degree of strength indeterminacy. The VHDL Standard Logic Package includes such a signal value data type, t wlogic, that includes 46 unique values. In this paper we provide a foundation for the t wlogic values and their resolution function that provides a possible link between simulation and theoremproving. A formalization of the low level signal values used by design tools also facilitates reasoning about CAD tools. Keyword Codes: Keywords: 1 Motivation Many VLSI design techniques involve the use of varying sized transistors for interconnecte...
Transistor Level Reliability Estimation Of Integrated Circuits
, 1995
"... The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly difficult to ensure highly reliable designs. Until now, the reliability of semiconductor chips ..."
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The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly difficult to ensure highly reliable designs. Until now, the reliability of semiconductor chips has been parametrized by the logic family; the operating voltage, temperature, and environment; and the level of integration of the component. Thus, to obtain highly reliable systems, it was often necessary to limit the number of transistors. An attractive and potentially important extension to the analysis of circuit reliability is to account for the connectivity of the individual internal components. For circuits in Complementary Metal Oxide Silicon (cmos) technology, this reliability analysis is accomplished by modeling open and shorted transistors, "stuckat" wires, and failed power and ground sources. Direct analysis of the reliability of a circuit by exhaustive enumeration of all fau...
A General Discrete Formalization of CMOS Transistor . . .
"... . Most discrete switchlevel CMOS models assume that switches (transistors) are perfect that is, the e ects of threshold voltages on signals are neglected in the discrete description of circuit behavior. While in some formalizations an attempt has been made to model these e ects, the main disadvan ..."
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. Most discrete switchlevel CMOS models assume that switches (transistors) are perfect that is, the e ects of threshold voltages on signals are neglected in the discrete description of circuit behavior. While in some formalizations an attempt has been made to model these e ects, the main disadvantage of these approaches is that for each design rule regarding imperfectness of switches a di erent model is re uired, as a result of which the circuit behavior as a whole must be evaluated again. The formalization presented here o ers a good separation of concerns in this respect, since the e ects of imperfectness of switches can be calculated separately from the abstracted circuit behavior. Furthermore, the formalization is general in the sense that it can be used in each discrete switchlevel CMOS model, and then leads to a more general and more accurate description of circuit behavior. Keywords Threshold voltages, Discrete switchlevel models, Discrete CMOS verification INTRODUCTION P...