Turbo decoding is a step towards ana- log because it uses soft-in/soft-out decoders. The next step is to go fully analog by exchanging extrinsic in- formation in continuous time ('flooding'). The component decoders are implemented in analog VLSI (a simple chip exists in 0.25/ra BiCMOS technology) and perform trellis or message passing decoding in continuous time while interconnected by an interleaver network. Simulation results for 'turbo' receivers with Hamming, tailbiting convolutional, DECPSK and multipath channel codes have shown that the performance is comparable with digital 'turbo' decoders. The advantage with analog 'turbo' networks is that they operate at much higher speed, have a smaller size and have much less power consumption than their digital counterparts.

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations with probabilities are naturally carried out by elementary transistor circuits. As an illustrative example, a complete decoder circuit for a simple tail-biting trellis code is given. Practical implementation issues such as device and thermal mismatch are also discussed. 1. INTRODUCTION Recently, it has been shown that very simple transistor circuits may be used to implement the basic computations of iterative decoders [1]. This paper presents an application of this new type of analog computing network. Such networks are not only especially suitable for decoding stat...

`Soft-in/soft-out' decoding of block and convolutional codes is done via analog, nonlinear and parallel networks. The theory for direct and trellis-based networks is described along with a network realisation of the APP BCJR algorithm. We report a prototype implementation in VLSI of an analog decoder for a tailbiting convolutional code showing the same performance as the classical processor type implementation, however with a considerable advantage in speed and power consumption with respect to the classical implementation by a digital processor.

Introduction In 1998, Hagenauer [6, 7] and Loeliger et al. [9] independently proposed to decode error correcting codes by analog electronic networks. In contrast to previous work on analog Viterbi decoders (e.g. Shakiba et al. [15] and several others before, see [10]), the work both by Hagenauer and by Loeliger et al. was inspired by "turbo"-style decoding of codes described by graphs [5, 16, 17]. Large gains, in terms of speed or power consumption, over digital implementations were envisaged. More complete accounts on these new analog decoders were given in [8] and [10, 11]. Since 1998, much e#ort has been spent towards turning these ideas into working chips. While only decoders of "toy" codes have so far been successfully manufactured, extensive simulations of such circuits have not revealed any fundamental problems. Some progress has also been made in analyzing the e#ects of transistor mismatch [12]. While much remains to be learned, this author feels confident that analog decoder

Motivated by the potential to reuse the architecture in place for an analog sum-product decoder, and thus reduce circuit space, we show how an encoder may be constructed for a class of reversible LDPC codes. We review the design of the analog sum-product decoder for subthreshold CMOS current mode operation and then show how the architecture may be reused for encoding. The encoder circuit operates by performing the Jacobi method for iterative matrix inversion of finite field matrices. We investigate both continuous and discrete time approaches. With the addition of only simple components into the sum-product decoder variable nodes, we provide a novel design for a time multiplexed analog codec.

The maximum a posteriori (MAP) decoding algorithm for convolutional codes is reformulated in terms of probabilities and log-likelihood ratios. This is shown to be a precise circuit description of an analog decoder in terms of currents and voltages which inspires different circuit designs. I. INTRODUCTION Recently several proposals for analog decoders were made in [1], [2], [3], [4], [5], which is in contrast to common practice where decoding is performed by digital processors. The implementation of `soft-in/soft-out' decoders which accept soft input from the demodulator and deliver soft output for the information bits require that soft values are processed throughout the decoder [6]. Such decoders are useful for serial or parallel concatenated decoding schemes, e.g., `turbo'-decoding. In the digital domain the soft values are represented by a hard decision for the corresponding bit combined with additional quantized reliability information about the decision. Especially in combination...

Abstract—The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results. Index Terms—Analog processing, floating-gate (FG) MOS transistors, parallel concatenated convolutional codes (PCCC), soft input soft output (SISO), translinear circuits, turbo codes. I.

: The sum-product algorithm (probability propagation) can be mapped directly into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes. Patent application pending. This research was supported by the Swiss National Science Foundation under Grant 21-49619.96. a Endora Tech AG, Gartenstrasse 120, CH-4052 Basel, Switzerland. E-mail: haloeliger@access.ch b ISI / Electrical Eng., ETH Zentrum, CH-8092 Zurich, Switzerland. E-mail: lustenbe@isi.ee.ethz.ch c ISI / Electrical Eng., ETH Zentrum, CH-8092 Zurich, Switzerland. E-mail: helfenst@isi.ee.ethz.ch d Endora Tech AG, Gartenstrasse 120, CH-4052 Basel, Switzerland. E-mail: ftarkoey@access.ch 1 Introduction Algebraic coding theory and digital VLSI have long been known to be a happy match: the common primitive digital circuits (binary memory cells and logic gates) are ideally suited for finite-field arithmetic. Such a match does no...

The Soft-Input Soft-Output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

In order to reach the Shannon limit, researchers have found more e#cient error control coding schemes. However, the computational complexity of such error control coding schemes is a barrier to implementing them. Recently, researchers have found that bioinspired analog network decoding is a good approach with better combined power/speed performance than its digital counterparts. However, the lack of CAD (computer aided design) tools makes the analog implementation quite time consuming and error prone. Meanwhile, the performance loss due to the nonidealities of the analog circuits has not been systematically analyzed. Also, how to organize analog circuits so that the nonideal e#ects are minimized has not been discussed.