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12
Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer
, 1997
"... This paper demonstrates the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8m CMOS process and operating as both a downconverter and an upconverter. As a downconverter with an RF input of 1.9 GHz, the mixer has a single sideband noise figure as low as 7.8 dB and achiev ..."
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This paper demonstrates the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8m CMOS process and operating as both a downconverter and an upconverter. As a downconverter with an RF input of 1.9 GHz, the mixer has a single sideband noise figure as low as 7.8 dB and achieved downconversion gain for supply voltages as low as 1.8 V. As an upconverter, the mixer demonstrates 10 dB of conversion gain at an RF frequency of 2.4 GHz with an applied local oscillator (LO) power of 07 dBm and LORF/LOIF isolation of at least 30 dB. Upconversion gain was achieved over a 5GHz bandwidth and at supply voltages as low as 1.5 V. The mixer presented demonstrates the lowest single side band noise figure for a CMOS doubly balanced downconverting mixer and the highest frequency of operation for a mixer fabricated in CMOS technology to date. Index Terms CMOS integrated circuits, frequency conversion, microwave measurement, microwave mixer, mixer noise, mixers, power dema...
A design methodology for highlyintegrated lowpower receivers for wireless communications
, 2001
"... ..."
Time Resolution of NMOS Sampling Switches Used on LowSwing Signals
 IEEE Journal of SolidState Circuits
, 1998
"... A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8m transistor. We present an expression for the aperture time for an NMOS ..."
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Cited by 6 (0 self)
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A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8m transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8m standard CMOS is 21 ps (48 Gb/s). SPICE simulations agree with the theory. Transient twodimensional (2D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8m standard CMOS process show successful sampling of every thirtysecond bit of a 5Gb/s data stream. Index TermsAperture time, CMOS integrated circuits, highspeed integrated circuits, sample and ...
Feedback linearization of RF power amplifiers
, 2003
"... that I have read this dissertation and that in my opinion it is fully adequate, ..."
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Cited by 4 (2 self)
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that I have read this dissertation and that in my opinion it is fully adequate,
A Parallel Structure for CMOS FourQuadrant Analog Multipliers and Its Application to a 2GHz RF Downconversion Mixer
 IEEE Journal of solid state circuits
, 1998
"... A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier ..."
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Cited by 2 (0 self)
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A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepoly doublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximumscale input 500mVPP at both multiplier inputs. The 03dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 01dB conversion gain, 2....
CONTENTS
"... – Basic concepts and definitions – Analytic signals and Hilbert transforms – Frequency translations and mixing ..."
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– Basic concepts and definitions – Analytic signals and Hilbert transforms – Frequency translations and mixing
A 900MHz CMOS Bandpass Amplifier for Wireless Receivers
, 1999
"... This dissertation describes the design of a CMOS 900MHz bandpass amplifier that is suitable for RF transceivers. The work employs the stateofart inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input ..."
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This dissertation describes the design of a CMOS 900MHz bandpass amplifier that is suitable for RF transceivers. The work employs the stateofart inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input matching networks onchip. A Qcompensation circuit is included to achieve a 25MHz 3dB bandwidth. Besides, a center frequency tuning circuit is also embedded to compensate for frequency deviations due to process variations. In the first prototype, a secondorder bandpass amplifier had been fabricated in standard 0.8 μm singlepoly, triplemetal CMOS process (HP SCN26G) provided by MOSIS ®. With a 3V supply, at 950MHz and a 3dB bandwidth of 25MHz, the measured voltage gain is 26 dB and the input S 11 is13 dB. Under the same baising condition, the input thirdorder intermodulation product (IIP 3) and inputreferred 1dB compression point (P o,1dB) are 21.5 dBm and31.5 dBm respectively. The image rejection at 140MHz away from the desired signal is 20 dB. In addition, the Q of the amplifier can be tuned from around 2 to infinity and the center frequency can also be varied from 930 MHz to 1040 MHz. On the grounds that the measured
RF Integrated Circuits in Standard CMOS Technologies
, 1996
"... Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep submicron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research gr ..."
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Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep submicron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance downconverters, low phase noise voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The research has already demonstrated fully integrated receivers and VCO circuits with no external components, nor tuning or trimming. Further research on low noise amplifiers, upconverters, synthesizers and power amplifiers will hopefully result in CMOS RF circuits for fully integrated transceivers for telecommunication applications. 1. Introduction A few years ago the world of wireless communications and its applications started to grow rapidly. The driving force for this is the introduction of digital coding and digital s...
A 3.3 V 30 mW 200 MHz CMOS Upconversion Mixer using Replica Transconductor
"... The lower transconductance of CMOS devices limits the implementation of upconversion mixer especially for lower loads. In this paper, a power efficient linear upconverter is presented. Using replica transconductor, the linear range is extended up to the limit. The circuit was implemented using 0 ..."
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The lower transconductance of CMOS devices limits the implementation of upconversion mixer especially for lower loads. In this paper, a power efficient linear upconverter is presented. Using replica transconductor, the linear range is extended up to the limit. The circuit was implemented using 0.8 m CMOS technology. The power consumption is 30 mW with 3.3 V supply. The mixer operates properly above 200 MHz. 1. Introduction The applications of CMOS technology in communication devices such as mixers[1], data converters and filters have proved successful. CMOS devices show better integration density, lower cost and better compatibility with digital circuitry compared to BJT ones. But inherent lower transconductance still limits the scope, especially in driving low impedance loads at high frequency operation. The upconversion mixer is one of these applications where the high frequency output drives low impedance loads. The IF upconversion mixer for modern cellular or PCS system ma...
Mixer Topology Selection for a MultiStandard
, 2002
"... In this paper, a mixer topology selection for a multistandard high imagereject frontend is presented. The receiver is intended to work for Digital Enhanced Cordless Telephone (DECT) systems (at 1.9 GHz and 2.4 GHz) and for Bluetooth (at 2.4 GHz). It will be implemented in 18 m CMOS technology. ..."
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In this paper, a mixer topology selection for a multistandard high imagereject frontend is presented. The receiver is intended to work for Digital Enhanced Cordless Telephone (DECT) systems (at 1.9 GHz and 2.4 GHz) and for Bluetooth (at 2.4 GHz). It will be implemented in 18 m CMOS technology. A doublequadrature lowIF architecture is employed because it can provide a high image rejection and flexibility for different standards. Building block specifications are optimized in order to achieve high image rejection and high sensitivity. Since the downconverter is the core of the frontend, it is necessary to select a high performance mixer topology that can provide low noise figure, high voltage gain, low power consumption and moderate linearity. Instead of simply using standard Gilbert cell and focus on its optimization, as it is quite often done in the literature, three mixer topologies, are examined. The evaluation is done analytically and by simulations with SpectreRF. A novel folded switching mixer topology achieves the best performance. With this topology the following simulation results are achieved: noise figure (NF) 14 dB, voltage gain (G) 17 dB, linearity (IIP 3 ) 1 dBm with a power consumption of 4 5 mW at the operating frequency of 2 5 GHz. Good matching between expected and simulated results is observed. A low voltage operation, which implies robustness for technology scaling, is also considered. At the end the final results are reported and the most promising topology is selected.