Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This implies that the number of simulations which must be performed in order to find the maximum power dissipation is exponential in the number of inputs to the network. In this paper we show that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, we give algorithms for transforming the problem to a weighted rnax-satisfiability problem, and then present exact and approximate algorithms for solving weighted max-satisfiability. Algorithms for constructing the max-satisfiability problem for both dynamic and static CMOS, where for the latter dissipation caused by glitching is considered, are presented. Also, we present efficient exact and approximate methods for solving weighted max-satlsfiability and show that these methods are viable for large-scale problems through examination of experimental results.

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