FPGA-based reprogrammable systems are revolutionizing some forms of computation and digital logic. As a logic emulation system they provide orders of magnitude speedup over software simulation. As a custom-computing machine they achieve the highest performance implementation for many types of applications. As a multi-mode system they yield significant hardware savings and provide truly generic hardware. In this paper we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems, as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.

The emergence of static memory--based FPGAs that are capable of being dynamically reconfigured, i.e. partially reconfigured while active, has resulted in research into new methods of digital systems synthesis. At present, however, there are virtually no CAD tools to support the design of digital systems using dynamic reconfiguration. This paper reports on an investigation of new simulation tools and the development of a new simulation technique for dynamically reconfigurable systems. I. INTRODUCTION The use of FPGAs has been classified broadly into three main categories: rapid prototyping, system implementation, and dynamically reconfigurable subsystems. The last of these areas has been described as being "perhaps the most innovative (application) for FPGAs and still in its infancy" [1]. This paper reports on the development of a new simulation method for FPGA--based systems which are dynamically reconfigurable. The work is part of a structured programme of research to investigate th...

onald Minnich, Douglas Sweely, and Daniel Lopresti. Building and using a highly parallel programmable logic array. IEEE Computer, pages 81--89, January 1991. [13] David E. Goldberg. Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley Publishing Company, Incorporated, Reading, Massachusetts, 1989. [14] John J. Grefenstette and James E. Baker. How genetic algorithms work: A critical look at implicit parallelism. In J. David Schaffer, editor, Proceedings of the Third International Conference on Genetic Algorithms, pages 20--27. Morgan Kaufmann Publishers, Incorporated, June 1989. [15] Paul Kenyon, Sharad Seth, Prathima Agrawal, Andrea Clematis, Gabriella Dodero, and Vittoria Gianuzzi. Programming pipelined CAD applications on message passing architectures. Submitted for publication, 1993. [16] Jonah McLeod. Reconfigurable computer changes architecture. Electronics, page 5, April 1994. [17] Mentor

The requirements of a general purpose massively parallel processing system are outlined. The suitability of a finegrained self-reconfigurable system to general massively parallel processing is shown. A new type of self-reconfigurable device called the PIG is introduced, and details of its design and operation are explained. The PIG's uniqueness compared to other reconfigurable systems is discussed. This uniqueness is further illustrated through specific examples of PIG circuits. An application of the PIG to evolvable hardware is described. Further potential applications are discussed. Plans for future work, including options for building a large-scale PIG are discussed.

The ability for providing a hardware platform which can be customized on a per-application basis under software control has established Reconfigurable Computing (RC) as a new computing paradigm. A machine employing the RC paradigm is referred to as a Field-Programmable Custom Computing Machine (FCCM). So far, the FCCMs have been classified according to implementation criteria. For the previous classifications do not reveal the entire meaning of the RC paradigm, we propose to classify the FCCMs according to architectural criteria.

We present a prototyping environment with special benefit for hardware/software codesign which we use as target architecture in the COBRA project . This architecture is very flexible, easy extensible, and provides a high gate complexity. It supports standard processor integration as well as processor emulation.

This paper describes a Reconfigurable Compute Engine (the Data-Flow Functional Computer, or DFFC) developed at ETCA and dedicated to rapid prototyping of real-time vision automata. The Computer consists of a regular 3D array of very coarse grain applicationspecific FPGA called the Field-Programmable Operator Array (FPOA); each FPOA includes 2 Configurable Data-Paths (CDP) and 10 Input/Output Ports (IOP). Specific development tools allow an easy and efficient use of the Computer: a high-level description (in a functional language) is compiled into a DFFC configuration using an Operator Library. Several significant applications (connected component labeling, non-linear filtering, colored object tracking) have been implemented using our tools. An environment for automatic derivation of vision automata from a DFFC configuration is currently under development. 1 Introduction Field-Programmable Gate Arrays have seen widespread use as reconfigurable computing elements in the past few years [...

FPGA systems outperform many ASIC and super computer systems through effective use of the reconfigurable resource. Reusing design effort across different applications requires a standard, flexible software environment. Driving FPGA systems from ANSI C is possible using lcc (an ANSI C compiler) targeted at an FPGA system and dasm (a retargetable, flexible assembler) . The compiler supports custom hardware capabilities of FPGA systems, as well as all constructs of C. The assembler reads instruction definitions at assemble time, allowing the user to add new custom hardware functions which dasm can assemble correctly to an instruction stream the hardware executes. A source code debugger has been implemented for this system. 1 Introduction FPGAs are capable of achieving high performance on many application-specific tasks. In many cases performance achievable with FPGAs on certain applications exceeds comparable ASIC designs or even super computers[2, 7]. One approach used in obtaining this...

A genetic algorithm (GA) is an optimization method based on natural selection. Genetic algorithms have been applied to many hard optimization problems including VLSI layout optimization, boolean satisfiability, power system control, fault detection, control systems, and signal processing. GAs have been recognized as a robust general-purpose optimization technique. But application of GAs to increasingly complex problems can overwhelm software implementations of GAs, causing unacceptable delays in the optimization process. This is true of any non-trivial application of GAs if the search space is large or if real-time performance is necessary. It follows that a hardware implementation of a GA is desirable for application to problems too complex for software-based GAs. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1--2 orders of magnitude have been observed when frequently used software routines were implemented in hardware...

Routing Architecture and Layout Synthesis for Multi-FPGA Systems Doctor of Philosophy, 1999 Mohammed A. S. Khalid Department of Electrical and Computer Engineering University of Toronto Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected.