The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to express each algorithm's dependencies and to support automatic synthesis, partitioning, and mapping to a reconfigurable computer. Within this framework, each benchmark is portably designed in both C and Behavioral Verilog and scalably parameterized to consume a range of hardware resource capacities. To establish initial benchmark ratings, we have targeted a commercial logic emulation system based on virtual wires technology to automatically generate designs up to millions of gates (14 to 379 FPGAs). Because the virtual wires techniques abstract away machine-level details like FPGA capacity and interconnect, our hardware target for this system is an abstract reconfigurable logic fabric with memorymapped host I/O. We report initial speeds in the range of 2X to 1800X faster than a 2.82 SPECint95 SparcStation 20 and encourage others in the field to run these benchmarks on other systems to provide a standard comparison.

FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices. 1 Introduction FPGAs offer many advantages for many kinds of applications and present new opportunities for system design [DeHon 94], but their main disadvantages are the limited number of cells available on a single chip and the difficulty of performing global communication. It is important that the available cells are utilized efficiently . One way to do this is to design circuits with a low level schematic editor and manually configure the cells and routing elements. Although this method allows the realization of highly optimised hardware, it has several shortcomings. Design at the gate level is error prone, and c...

We present a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-andconquer structure, with the "divide" and "merge" phases carried out by a general-purpose processor while the "conquer " phase is handled by application-specific hardware. The partitioning strategy has been captured in a simple functional language, and we have automated the production of partitioned programs in this language. Our approach has been tested on an FPGA-based system using a number of computer vision algorithms,including the Canny edge detector, and the performance is compared against executing the programs on the PC host. 1 Introduction The objective of our research on hardware-software codesign is to develop systems containing both hardware and software components with higher quality, in shorter time, and at lower cost than existing ones. Recent advances in programmable logic, particularly Field-Programmable Gate Arra...

We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for parametrised partitioning into hardware and software can be captured concisely in this framework, and their validity can be checked using algebraic reasoning. The method has been used to guide the development of prototype compilers capable of producing, from a Ruby expression, a variety of implementations involving fieldprogrammable gate arrays (FPGAs) and microprocessors. The viability of this approach is illustrated using a number of examples for two reconfigurable systems, one containing an array of Algotronix devices and a PC host, and the other containing a transputer and a Xilinx device. 1 Introduction Although it has been known for many years that, from a functional point of view, there is little distinction between hardware and software, in current practice they are mostly developed using very different m...

. This paper reports recent work on the automatic design and implementation of microprocessors to suit particular applications. We use our own hardware compilation system to produce synchronous hardware implementations of parallel programs and have constructed platforms incorporating Field Programmable Gate Array and transputer components to host such implementations. Our chosen language, Handel, is essentially a subset of occam with as few extensions as necessary to address the special nature of hardware implementations. The system reported here can take a Handel program and, rather than mapping it directly to hardware, will first transform it into a custom microprocessor, expressed as another Handel program, together with a machine code program. The hardware compiler is then invoked to construct the resulting application-specific microprocessor. This approach may have benefits for applications where the kernel, or `inner loop', is too complex to be implemented as parallel hardware, b...

The declarative language Ruby provides a coherent framework for representing and developing designs. Sketching diagrams for Ruby programs by hand is, however, time-consuming and error-prone. This paper describes a design sketcher which automates the production of a diagram from a Ruby description. 1 INTRODUCTION Text-based languages, such as VHDL, 3 are becoming increasingly popular for developing designs. Their popularity is mainly due to their facilities for parametrising designs, and it is a great bonus if both behaviour and structure can be expressed in a single notation. Moreover, pictorial representations such as circuit schematics can be tedious to create and to modify. Providing visual aid in hardware design is, nevertheless, important. Circuit diagrams, when appropriately drawn, make explicit the basic structure and size of components, allowing designers to obtain rapidly an overview of a design and to locate specific parts on which they can focus. There have been attempts ...

Hardware architectures for feature selection

Reconfigurable logic devices such as the FPGA have brought about a revolution in the field of hardware design. The reduction in development costs has had a huge impact on broadening the scope of applications for which a hardware implementation is a realistic possibility. Current FPGA devices run to many millions of gates, giving a huge potential for efficiency gains, benefiting from the inherently parallel nature of hardware circuits. These devices continue to grow in size, to the end that we can now seriously consider implementing even large scale systems purely in reconfigurable logic. Despite these advances, we find ourselves somewhat lacking in the tools and methodologies required to fully exploit this potential. Issues of hardware implementation and parallelism intro-duce significant complexity into the design process. We argue that without the correct approach, not only will this potential be under used, but the inherent complexity will undermine people’s

this document which have been, and continue to be, a genuinely inter-disciplinary collaborative venture. In addition, Tony Hoare and Bob McLatchie have been strongly supportive of this work in every way, Bernard Sufrin has provided us with much help on the use of Standard ML, Richard Bird has contributed new algorithms for shared expression extraction, Mark Josephs and Jelio Yantchev have provided useful input on asynchronous models and routing networks. References