Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today's systems typically are sufficient, quality of service (QoS) guarantees as required for handling such data types cannot be provided by these systems in adequate ways. We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission delays. Similar to the ATM technology Switcherland provides QoS guarantees with the help of service classes, that is, data transfers are characterized as variable bit rate traffic or constant bit rate traffic. However, unlike LAN technologies, Switcherland is optimized for cluster computing in that (i) it serves as a backplane interconnection fabric as well as a LAN, (ii) it extends support for service classes by also covering the end nodes of the ne...

We report on a class of high-rate dc-free codes, called multimode codes, where each source word can be represented by a codeword taken from a selection set of codeword alternatives. Conventional multimode codes will be analyzed using a simple mathematical model. The criterion used to select the "best" codeword from the selection set available has a significant bearing on the performance. Various selection criteria are introduced and their effect on the performance of multimode codes will be examined. I.

Molecular dynamics is a computationally intensive technique used in biomolecular simula-tions. We are building a hardware accelerator using a multiprocessor approach based on FPGAs. One key feature being leveraged is the availability of multi-gigabit serial transceiver technology (SERDES) available on the latest FPGAs. Computations can be implemented by a dedicated hardware element or a processor running software. Communication is imple-mented with a standard hardware interface abstraction. The actual communication is done via asynchronous FIFOs, if the communication is on-chip, or via Ethernet and SERDES, if the communication is between chips. The use of Ethernet is significantly slower than the SERDES, but allows for prototyping of the architecture using off-the-shelf develop-ment systems. A reliable, high-speed inter-FPGA communication mechanism using the SERDES channels has been developed. It allows for the multiplexing of multiple channels between chips. Bi-directional data-throughput of 1.918Gbps is achieved on a 2.5Gbps link and compared against existing communication methods. iii

This paper presents a study of the errors observed when an optical Gigabit Ethernet link is subject to attenuation. We use a set of purpose-built tools which allows us to examine the errors observed on a per-octet basis. We find that some octets su#er from far higher probability of error than others, and that the distribution of errors varies depending on the type of packet transmitted.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

ii iv Today’s high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient, and the power and area constraints make standard digital communication approaches infeasible. This thesis presents a system-level link design approach, tightly integrating the noise and channel properties with communication algorithms and circuit-level power and speed constraints. After describing the issues that high-speed I/Os need to overcome, we create a model that correctly represents the statistics of the various noise sources that affect the system’s performance. Our new link model maps the timing noise into effective voltage noise revealing the critical impact of high-frequency transmit jitter. This model estimates the performance limits of the system, and indicates the components which most limit the link

General purpose computing architectures are being called on to work on a more diverse application mix every day. This has been fueled by the need for reduced time to market and economies of scale that are the hallmarks of software on general purpose microprocessors. As this application mix expands, application domains such as bitlevel computation, which has primarily been the domain of ASICs and FPGAs, will need to be effectively handled by general purpose hardware. Examples of bit-level applications include Ethernet framing, forward error correction encoding/decoding, and efficient state machine implementation. In this paper we compare how differing computational structures such as ASICs, FPGAs, tiled architectures, and superscalar microprocessors are able to compete on bitlevel communication applications. A quantitative comparison in terms of absolute performance and performance per area will be presented. These results show that although modest gains (2-3x) in absolute performance can be achieved when using FPGAs versus tuned microprocessor implementations, it is the significantly larger gains (2-3 orders of magnitude) that can be achieved in performance per area that will motivate work on supporting bit-level computation in a general purpose fashion in the future.

the degree of Doctor of Philosophy. Advances in integrated circuit technologies permit faster clocking speed and increased logic density in chips. However, advances in chip packaging technologies have not kept pace; hence the number of input/output pins and input/output bandwidth per chip has increased less rapidly. The resulting disparity creates the need for more bandwidth per pin. Single-ended signalling and simultaneous bidirectional signalling methods may each increase the bandwidth per pin by a factor of two. However, using these signalling methods poses challenges in compensating for additional noise sources and reduced noise rejection ratios. This work presents the architecture, circuit techniques, and test results for a single-ended simultaneously bidirectional interface capable of a total throughput of 8 Gigabits per second per pin. The interface addresses the noise reduction challenges by utilizing a pseudo-differential reference with noise immunity approaching that of a fully differential reference. Furthermore, noise generation is reduced by on-chip termination, and low-skew near-end outgoing signal echo cancellation. A test chip in a 0.35 micron digital CMOS technology uses these techniques for an eight bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gigabit per second per pin.

this paper we describe a system to show some limited effects on a static toy-car model and present techniques that can be used in similar setups. Our focus is on creating apparent motion for animation

The 8b/10b Encoder core implements the full code set proposed by A.X. Widmer and P.A. Franaszek 1. The code specifies the encoding of an 8-bit byte (256 unique data words) and an additional 12 special (or K) characters into a 10-bit symbol, hence the 8b/10b designation. The characteristics of the code scheme make it ideally suited for high-speed local area networks, computer links, or any serial data link. The code scheme is DC-balanced, which is of particular benefit for active gain, threshold setting and equalization of optical receivers. The code insures a limited run length, no more than 5 consecutive ones or zeros, and a guaranteed transition density, which permits clock recovery from the data stream. The special (K) characters are useful as packet delimiters. A subset of them, referred to as commas, are unique in that their bit pattern never occurs in a string of serialized data symbols and hence can be used to determine symbol boundaries at the receiving end. Additional rules embedded in the code design allow many errors to be detected at the receiving end. The combination of these features allows the receiving end of an encoded 8b/10b data stream to extract the bit rate clock, to determine symbol (and packet) boundaries, and to detect most transmission errors. This is all done with a comparatively low overhead of 25 percent (each 10-bit symbol contains 8 bits of information) versus, for example, a Manchester code with its 100 percent overhead. Because of its many features, the code has been used in the physical layer (PHY) of a number of current and emerging standards, including Fibre Channel, Gigabit Ethernet, and Rapid I/O, to name a few.