We introduce a shared data object, called a composite register, that generalizes the notion of an atomic register. A composite register is an array-like shared data object that is partitioned into a number of components. An operation of a composite register either writes a value to a single component or reads the values of all components. A composite register reduces to an ordinary atomic register when there is only one component. In this paper, we show that multi-reader, single-writer atomic registers can be used to implement a composite register in which there is only one writer per component. In a related paper, we show how to use the composite register construction of this paper to implement a composite register with multiple writers per component. These two constructions show that it is possible to implement a shared memory that can be read in its entirety in a single snapshot operation, without using mutual exclusion. Keywords: atomicity, atomic register, composite register, conc...

A snapshot scan algorithm takes an "instantaneous" picture of a region of shared memory that may be updated by concurrent processes. Many complex shared memory algorithms can be greatly simplified by structuring them around the snapshot scan abstraction. Unfortunately, the substantial decrease in conceptual complexity is quite often counterbalanced by an increase in computational complexity. In this paper, we introduce the notion of a weak snapshot scan, a slightly weaker primitive that has a more efficient implementation. We propose the following methodology for using this abstraction: first, design and verify an algorithm using the more powerful snapshot scan, and second, replace the more powerful but less efficient snapshot with the weaker but more efficient snapshot, and show that the weaker abstraction nevertheless suffices to ensure the correctness of the enclosing algorithm. We give two examples of algorithms whose performance can be enhanced while retaining a simple m...

We define a class of operations called pseudo read-modify-write (PRMW) operations, and show that nontrivial shared data objects with such operations can be implemented in a bounded, wait-free manner from atomic registers. A PRMW operation is similar to a "true" read-modify-write (RMW) operation in that it modifies the value of a shared variable based upon the original value of that variable. However, unlike an RMW operation, a PRMW operation does not return the value of the variable that it modifies. We consider a class of shared data objects that can either be read, written, or modified by an associative, commutative PRMW operation, and show that any object in this class can be implemented without waiting from atomic registers. The implementations that we present are polynomial in both space and time and thus are an improvement over previously published ones, all of which have unbounded space complexity. Keywords: assertional reasoning, atomicity, atomic register, composite register, ...

Data sharing among tasks within multiprocessor real-time systems is a crucial issue. This report presents a fully asynchronous mechanism of sharing data between a single writer and multiple readers. The writer and all the readers are allowed to access the shared data asynchronously in a loop-free and wait-free manner because neither locking operations nor repeated actions of read-and-check are involved. Its implementation uses only (n + 2) buffer slots for n readers, and employs an atomic `Store-IfZero ' operation which can be easily simulated with the Compare-and-Swap instruction. Since neither writing nor reading the shared data imposes any effect upon other tasks in the system, this mechanism introduces no impact upon the timing behaviour of tasks. When employed by real-time applications, it helps to reduce blocking and priority inversion problems incurred by the commonly used lock-based synchronization mechanisms. 1 Introduction Data sharing is a basic approach to achieving inter...

A modified 4-slot asynchronous communication mechanism (ACM) using entirely selftimed circuits to implement the algorithm is presented here. Mutual exclusion elements are used to concentrate potential metastability to a couple of discrete points so that it can be resolved entirely within the mechanism itself, while the self-timed circuits allow the interface between the reader and writer processes and the mechanism to be minimised. Initial analyses show that this solution is more robust with regard to steering logic metastability, and can potentially run faster, than the original 4-slot solution. 2 Introduction writer data in shared memory control variables reader Figure 1 Asynchronous data communication mechanisms using shared memory and control variables. Data communication between concurrent processes often employ shared memory which may have access conflicts when the processes are not synchronised. The most obvious way to protect shared memory is to put it into a critical section ...

This report presents an approach to implementing fully asynchronous reader/writer mechanisms which addresses the problems of priority inversion and blocking among tasks within multiprocessor real-time systems. The approach is conceived from the concept of process consensus that the writer and the reader come to an agreement on accessing the shared data before proceeding to carry out their respective data operations. Because neither locking operations nor repeated actions of read-and-check are involved, the shared data can be accessed at any time by the writer and all the readers in a manner not only wait-free but also loop-free. In addition, data sharing through this approach introduces no impact upon either timing behaviour or schedulability of any task in the system. Hence the approach can help to remove priority inversion and blocking incurred by the commonly used lock-based synchronization mechanisms. 1 Introduction The implementation of shared data objects is a very important iss...

A naming protocol assigns unique names (keys) to every process...

This report presents an approach to realizing a three-slot asynchronous reader/writer mechanism in multiprocessor real-time systems. The mechanism allows both the reader and the writer to access the shared data object at any time without employing any conventional synchronization protocol. Its implementation takes advantage of the hardware supported Compare-and-Swap instruction to coordinate buffer accessing. Since there is no locking mechanism adopted in the approach, it is a non-blocking mechanism such that delay of either the reader or the writer imposes no effect upon the other. In addition, no repeated reading is needed by the reader. For real-time applications, this mechanism introduces no impact upon timing behaviour of tasks. It helps to reduce blocking and priority inversion problems incurred by the commonly used lock-based synchronization mechanisms. 1 Introduction Data sharing, which is a basic approach to achieving intertask communication within a variety of applications,...

Mutual exclusion is a topic that Leslie Lamport has returned to many times throughout his career. This article, which is being written in celebration of Lamport's sixtieth birthday, is an attempt to survey some of his many contributions to research on this topic.

Abstract We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components.