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36
Iterated Register Coalescing
 ACM Transactions on Programming Languages and Systems
, 1996
"... An important function of any register allocator is to target registers so as to eliminate copy instructions. Graphcoloring register allocation is an elegant approach to this problem. If the source and destination of a move instruction do not interfere, then their nodes can be coalesced in the inter ..."
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Cited by 165 (4 self)
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An important function of any register allocator is to target registers so as to eliminate copy instructions. Graphcoloring register allocation is an elegant approach to this problem. If the source and destination of a move instruction do not interfere, then their nodes can be coalesced in the interference graph. Chaitin's coalescing heuristic could make a graph uncolorable (i.e., introduce spills); Briggs et al. demonstrated a conservative coalescing heuristic that preserves colorability. But Briggs's algorithm is too conservative, and leaves too many move instructions in our programs. We show how to interleave coloring reductions with Briggs's coalescing heuristic, leading to an algorithm that is safe but much more aggressive. 1 Introduction Graph coloring is a powerful approach to register allocation and can have a significant impact on the execution of compiled code. A good register allocator does copy propagation, eliminating many move instructions by "coloring" the source tempor...
Optimal Spilling for CISC Machines with Few Registers
 In Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
, 2000
"... Register allocation based on graph coloring performs poorly for machines with few registers, if each temporary is held either in machine registers or memory over its entire lifetime. With the exception of shortlived temporaries, most temporaries must spill  including long lived temporaries that a ..."
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Cited by 78 (1 self)
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Register allocation based on graph coloring performs poorly for machines with few registers, if each temporary is held either in machine registers or memory over its entire lifetime. With the exception of shortlived temporaries, most temporaries must spill  including long lived temporaries that are used within inner loops. Liverange splitting before or during register allocation helps to alleviate the problem but prior techniques are sometimes complex, make no guarantees about subsequent colorability and thus require further iterations of splitting, pay no attention to addressing modes, and make no claim to optimality. We formulate the register allocation problem for CISC architectures with few registers in two parts: an integer linear program that determines the optimal location to break up the implementation of a live range between registers and memory, and a register assignment phase that we guarantee to complete without further spill code insertion. Our linear programming model ...
A New Proof Of The FourColour Theorem
 ELECTRON. RES. ANNOUNCE. AMER. MATH SOC
, 1996
"... The fourcolour theorem, that every loopless planar graph admits a vertexcolouring with at most four different colours, was proved in 1976 by Appel and Haken, using a computer. Here we announce another proof, still using a computer, but simpler than Appel and Haken's in several respects. ..."
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Cited by 38 (0 self)
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The fourcolour theorem, that every loopless planar graph admits a vertexcolouring with at most four different colours, was proved in 1976 by Appel and Haken, using a computer. Here we announce another proof, still using a computer, but simpler than Appel and Haken's in several respects.
Experiments with Parallel Graph Coloring Heuristics
 In (Johnson & Trick
, 1994
"... We report on experiments with a new hybrid graph coloring algorithm, which combines a parallel version of Morgenstern's SImpasse algorithm [20], with exhaustive search. We contribute new test data arising in five different application domains, including register allocation and class scheduling ..."
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Cited by 27 (0 self)
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We report on experiments with a new hybrid graph coloring algorithm, which combines a parallel version of Morgenstern's SImpasse algorithm [20], with exhaustive search. We contribute new test data arising in five different application domains, including register allocation and class scheduling. We test our algorithms both on this test data and on several types of randomly generated graphs. We compare our parallel implementation, which is done on the CM5, with two simple heuristics, the Saturation algorithm of Br'elaz [4] and the Recursive Largest First (RLF) algorithm of Leighton [18]. We also compare our results with previous work reported by Morgenstern [20] and Johnson et al. [13]. Our main results are as follows. ffl On the randomly generated graphs, the performance of Hybrid is consistently better than the sequential algorithms, both in terms of speed and number of colorings produced. However, on large random graphs, our algorithms do not come close to the best colorings found ...
Adaptive Explicitly Parallel Instruction Computing
, 2000
"... Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set while generating code for a given application. Often this instruction set ..."
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Cited by 15 (2 self)
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Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set while generating code for a given application. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. 1. Can application performance be improved if the compiler had the freedom to pick the instruction set on a per application basis? 2. Can we build costeffective processors that provide the ability to efficiently emulate compiler determined instruction sets and yet are not application specific? 3. Given that the desired processor capabilities are feasible, can the compiler determine an optimal set of instructions for a given application and generate code that can effectively exploit the processor capabilities? In this thesis, we provide sufficient evidence to answer these questions in the affirmative. Through a combination of architectural innovations and novel compilation techniques, this dissertation demonstrates that it is possible to attain significant improvement in performance, up to an order of magnitude in some cases, on general purpose and multimedia applications over comparable fixed ISA processors. We propose classes of microprocessors that allow application programs to add and subtract functional units yielding a dynamically varying instruction set interface to the running application without compromising current compatibility model. First half of this dissertation describes this novel class of architectures, focusing on a specific subclass called Adaptive Explicitly Parallel Instruction Computing (AEPIC) architectures...
Coloring Maps And The Kowalski Doctrine
 Formalizing Common Sense  Papers by John McCarthy
, 1982
"... It is attractive to regard an algorithm as composed of the logic determining what the results are and the control determining how the result is obtained. Logic programmers like to regard programming as controlled deduction, and there have been several proposals for controlling the deduction expr ..."
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Cited by 8 (0 self)
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It is attractive to regard an algorithm as composed of the logic determining what the results are and the control determining how the result is obtained. Logic programmers like to regard programming as controlled deduction, and there have been several proposals for controlling the deduction expressed by a Prolog program and not always using Prolog's normal backtracking algorithm. The present note discusses a map coloring program proposed by Pereira and Porto and two coloring algorithms that can be regarded as control applied to its logic. However, the control mechanisms required go far beyond those that have been contemplated in the Prolog literature. Robert Kowalski (1979) enunciated the doctrine expressed by the formula 1 ALGORITHM = LOGIC + CONTROL The formula isn't precise, and it won't be precise until someone proposes a precise and generally accepted notion of how control is to be added to an expression of the logic of a program. Nevertheless, the idea is attractive,...
Uncolorable Mixed Hypergraphs
 Discrete Applied Math
, 1997
"... . A mixed hypergraph H = (X; A; E) consists of the vertex set X and ..."
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Cited by 7 (5 self)
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. A mixed hypergraph H = (X; A; E) consists of the vertex set X and
Formal Verification of Coalescing GraphColoring Register Allocation
, 2010
"... Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less faithfully) the imperative algorithm published in 1996. Several mistakes have been found in some of these implementati ..."
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Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less faithfully) the imperative algorithm published in 1996. Several mistakes have been found in some of these implementations. In this paper, we present a formal verification (in Coq) of the whole IRC algorithm. We detail a specification that can be used as a reference for IRC. We also define the theory of registerinterference graphs; we implement a purely functional version of the IRC algorithm, and we prove the total correctness of our implementation. The automatic extraction of our IRC algorithm into Caml yields a program with competitive performance. This work has been integrated into the CompCert verified compiler.
An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
, 2007
"... This paper presents a new register assignment heuristic for procedures in SSA Form, whose interference graphs are chordal; the heuristic is called optimistic chordal coloring (OCC). Previous register assignment heuristics eliminate copy instructions via coalescing, in other words, merging nodes in t ..."
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This paper presents a new register assignment heuristic for procedures in SSA Form, whose interference graphs are chordal; the heuristic is called optimistic chordal coloring (OCC). Previous register assignment heuristics eliminate copy instructions via coalescing, in other words, merging nodes in the interference graph. Node merging, however, can not preserve the chordal graph property, making it unappealing for SSAbased register allocation. OCC is based on graph coloring, but does not employ coalescing, and, consequently, preserves graph chordality, and does not increase its chromatic number; in this sense, OCC is conservative as well as optimistic. OCC is observed to eliminate at least as many dynamically executed copy instructions as iterated register coalescing (IRC) for a set of chordal interference graphs generated from several Mediabench and MiBench applications. In many cases, OCC and IRC were able to find optimal or nearoptimal solutions for these graphs. OCC ran 1.89x faster than IRC, on average.