this article would inevitably be carrying out some kind of local search, given that it has been the authors' finding that the use of a low population size and very high number of generations gives better results. To explore this contention, consider the effect on the functionality of a chromosome when a single gene in a netlist chromosome is altered at random. The consequences in loss of functionality may be catastrophic as for instance, a primary output might, as a result, be connected to the wrong cell output. This observation implies that at the very least the local fitness landscape of a particular chromosome is very noisy. Another important factor here is the fact that the number of possible neighbours to a chromosome (defining a neighbour to be a chromosome which differs from the original in a single gene) is very large indeed. These two factors make it all the more surprising that low population sizes and high numbers of generations are more effective. One's sense of mystification is heightened when one recalls that elitism also improved the results. In an attempt to gain some insight into what is going on it is interesting to examine the history of gene changes of the best in the population as it develops from initially containing a large number of random elements to the final highly evolved form associated with possessing 100% functionality. Table 6.5 below shows the evolution of the best chromosome of the population. Each new improvement in fitness and the generation at which it occurred are also shown. In addition the fitness changes are shown and the number of different genes between chromosomes, where only genes which contributed to the functionality of the resulting circuit were counted (see also Figure 6.17). The chromosomes relate to a 3 x 4 geometry of ...

. The study of intrinsic hardware evolution relies heavily on commercial FPGA devices which can be configured in real time to produce physical electronic circuits. Use of these devices presents certain drawbacks to the researcher desirous of studying fundamental principles underlying hardware evolution, since he has no control over the architecture or type of basic configurable element. Furthermore, analysis of evolved circuits is difficult as only external pins of FPGAs are accessible to test equipment. After discussing current issues arising in intrinsic hardware evolution, this paper presents a new test platform designed specifically to tackle them, together with experimental results exemplifying its use. The results include the first circuits to be evolved intrinsically at the transistor level. 1 Introduction In recent years, evolutionary algorithms (EAs) have been applied to the design of electronic circuitry with significant results being attained using both computer simulations...

In this paper, we address the routability and analog performance issues involved in routing for array-based FPAAs that have single-segment horizontal and vertical routing resources. We then present FAAR (Field-programmable Analog Array Router) and describe a routing algorithm developed for the target array-based FPAA architecture. Sequential routing technique is used for routing multi-terminalnets as well as multiple nets. Multi-terminal nets are broken into two-terminal pairs and routed. We use the notion of resource demand as a measure of the effect of a net-route on the routing of the other nets, while the number of programmable switches and the net-crossings are used as the metrics of interconnect parasitics. We present experiments to study the effect of various parameters such as the number of nets, terminals, CABs and IO cells on the routing as well as the performance degradation. FAAR routes with high efficiency while keeping performance degradation small, and has considerably s...

of the work presented in this thesis has been previously published as listed below. Although some of these papers have co-authors, the work appearing in this thesis is entirely my own, with the exception of parts of chapter 3, which presents work jointly carried out by myself and Adrian Thompson. The respective contributions to this work will be explicitly stated at the beginning of the chapter. List of Previous Publications Kuntz, P., Layzell, P., & Snyers, D. (1997). A Colony of Ant-like Agents for Partitioning

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5mm x 3.5mm in a 0.8μm CMOS technology. 1.

In this paper we present a novel RAM-based field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog signals. The device is especially suitable for development and fast prototyping of mixed signal integrated applications. 1.

In this paper we present a novel field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog signals. The device is especially suitable for development and fast prototyping of mixed signal integrated applications.

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable.