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A 1.8V digitalaudio sigmadelta modulator in 0.8µm CMOS
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D con ..."
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Cited by 21 (0 self)
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Abstract — Oversampling techniques based on sigmadelta (ΣΔ) modulation offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters in a lowvoltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digitalaudio A/D conversion that operates from a single 1.8V power supply. A cascaded modulator that maintains a large fullscale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fullydifferential switchedcapacitor integrators employing different input and output commonmode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of commonmode levels, high power supply noise rejection, and low power dissipation are obtained through the use of twostage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8μm CMOS technology with metaltopolycide capacitors and NMOS and PMOS threshold voltages of +0.65V and –0.75V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5 V to 2.5 V, occupies an active area of 1.5 mm 2, and dissipates 2.5 mW from a 1.8V supply.
Design of a lowdistortion 22kHz fifthorder Bessel filter
 IEEE J. SolidState Circuits
, 1993
"... Abs&actA linearity improvement technique employing passive resistors and currentsteering MOS transistors as a variable resistance element is proposed to implement a lowdistortion filter in CMOS technology. This proposed implementation relies on the linearity of the passive resistors and the tunab ..."
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Cited by 5 (2 self)
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Abs&actA linearity improvement technique employing passive resistors and currentsteering MOS transistors as a variable resistance element is proposed to implement a lowdistortion filter in CMOS technology. This proposed implementation relies on the linearity of the passive resistors and the tunability of the currentsteering MOS transistors operating in the triode region to overcome the limited linearity performance in continuoustime electronically tunable filters. By using the existing systematic feedback loops in the active filters and placing the nonlinear elements inside the feedback, the distortion resulting from the nonlinear devices is greatly reduced by the filter loop gain. A 22kHz fifththorder Bessel filter, its dynamic range optimized by applying Karmarkar’s resealing algorithm and selftuned with a switchedcapacitor reference resistor, demonstrates better than –90dB THD with a 2kHz, 4 Vpp signal in 5V 2~m CMOS. I.
A 75mW 128MHz DSCDMA Baseband Demodulator for HighSpeed Wireless Applications
, 1998
"... A DSCDMA demodulator uses analog sampleddata signal processing to achieve a 75mW power dissipation and a 128MS/s processing rate in a 1.2m doublemetal doublepoly CMOS process. To demodulate the signal, a lowpower passive correlation technique is introduced that eliminates the integrating opa ..."
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Cited by 4 (0 self)
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A DSCDMA demodulator uses analog sampleddata signal processing to achieve a 75mW power dissipation and a 128MS/s processing rate in a 1.2m doublemetal doublepoly CMOS process. To demodulate the signal, a lowpower passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64chip correlators recover the 2Mb /s data stream from the doubly modulated [pseudorandom noise (PN) and Walsh] quadrature input signal. An onchip 10b pipelined ADC sampling at 8 MS/s follows the analog correlation to permit digital implementation of the acquisition and tracking algorithms.
A Low Oversampling Ratio 14b 500kHz ADC with a SelfCalibrated Multibit DAC
 IEEE J. SolidState Circuits
, 1996
"... Abstract — Deltasigma (16) analogtodigital converters (ADC’s) rely on oversampling to achieve highresolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500kHz 16 ADC is described t ..."
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Cited by 3 (0 self)
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Abstract — Deltasigma (16) analogtodigital converters (ADC’s) rely on oversampling to achieve highresolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500kHz 16 ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated digitaltoanalog converter (DAC) are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2"m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. I.
A Low Oversampling Ratio 14b 500kHz ΔΣ ADC with a SelfCalibrated Multibit DAC
"... Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC ..."
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Cited by 1 (0 self)
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Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated DAC are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Deltasigma (\Delta\Sigma) analogtodigital converters are well suited for low f...
CHARGEDOMAIN SAMPLING OF HIGHFREQUENCY SIGNALS WITH EMBEDDED FILTERING
"... Academic Dissertation to be presented with the assent of ..."
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Academic Dissertation to be presented with the assent of
A SingleChip Stereo Audio DeltaSigma A/D Converter with 117 dB Dynamic Range
, 2000
"... This paperdesc8j es the development of the first audio ADC to fulfill the above mentioned ..."
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This paperdesc8j es the development of the first audio ADC to fulfill the above mentioned
Linearity Improvement . . . ContinuousTime Filters
, 1994
"... ... or its variations. Also included in the filter implementation is a linear programming approach to optimize the dynamic range, under the constraint of a fixed capacitor area that is assumed to be the dominant factor in the total chip area. ..."
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... or its variations. Also included in the filter implementation is a linear programming approach to optimize the dynamic range, under the constraint of a fixed capacitor area that is assumed to be the dominant factor in the total chip area.