A time-varying theory of Volterra series is developed and applied in the sampled-data domain to solve for harmonic and intermodulation distortion of a MOS-based track-and-hold sampling mixer with a nonzero fall-time LO waveform. Distortion due to sampling error is also calculated. These results, when combined with the continuous-time solution, quantify harmonic and intermodulation distortion of a track-and-hold type mixer completely. Closed-form solutions are obtained. As a practical consequence, it is shown that for certain fall-time, the distortion of track-and-hold mixers can be better than what would be predicted by a simple application of time-invariant Volterra series theory. Index Terms--- Harmonic distortion, intermodulation distortion, intermediate frequency (IF), radio frequency (RF), timevarying Volterra series, track-and-hold sampling mixer. I. INTRODUCTION I NCREASING demand for digital wireless personal communication devices, and steady improvements in the MOS device ...

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Abstract—A low power PSK demodulator integrated circuit (IC) has been implemented using Silicon On Insulator (SOI) CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit A/D converter at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at UHF frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit A/D converter is below 1 mW for data rates up to 100 Kbps. Index Terms—Phase-Shift Keying (PSK), differential detection, space communications, symbol timing circuit, multirate, sampling. D I.

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We present a Switched-Current (SI) fourth-order bandpass SD modulator IC prototype. It uses fully-differential circuits in 0.8m CMOS technology to obtain a Dynamic Range (DR) larger than 55 dB at 2.5MHz center frequency with 30kHz bandwidth - in accordance to the requirements of AM digital receivers. The prototype incorporates a single-ended to fullydifferential current-mode buffer for testing purposes. The power consumption of the whole prototype (modulator plus buffer) is 60mW from a 5V supply voltage. 1 Introduction Prompted by the convenience to design mixed-signal chips using standard VLSI technologies, different authors have explored the application of switched-current (SI) circuits for analog -to-digital conversion [1][4]. Most of their effort have been focused on lowpass SD modulators (SDM) for frequencies in the range of audio [1][2]. A few works have also explored the use of SI circuits for larger frequencies [3][4]. Particularly, [3] reports a 4th-order lowpass (SDM) fea...

Distortion and noise due in a bottom-plate sampling mixer is analyzed. The method of Volterra series is applied in the analysis of harmonic distortion, which combines the effects of continuous time, time varying, and sampling distortions. Frequency domain analysis is applied in the analysis of thermal noise. The method of stochastic differential equation is used to solve for LO noise. These two noise effects, when combined with LO jitter, give a complete noise picture. The analysis is performed in sampled data domain. Explicit formulas are given to guide the design of bottom-plate sampling mixers.

This paper addresses some of the architectural limitations and concerns in the development of CMOS high frequency front-ends for wireless communication applications. Different architectures are evaluated as to how well their characteristics suite an all CMOS integrated solution. Also, the comparison aims at important parameters such as low cost, low power, and small feature size. Important receiver architecture characteristics are summarized and compared. It is argued that digital generation of I/Q signal paths provides for a possible performance improvement. To accomplish the IF digitizing a bandpass Delta-Sigma Converter is suggested as a potential solution. I

Abstract — In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture. A bandpass Σ ∆ ADC is used for the analog to digital conversion process. An accurate and realistic model of the clock jitter in bandpass Σ ∆ ADC is implemented. Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both phase and waveform noise. It is shown that for the case of sampling at IF stage, the effect of waveform noise is quite small and negligible compared to the phase noise effect. Therefore, an estimation and compensation method based on the existing phase noise compensation method is proposed for alleviating the effect of clock jitter. Simulation results are presented, showing the significant performance gain of our proposed algorithm, providing a new and innovative way of dealing with the clock jitter problem of bandpass A/D conversion in OFDM systems. Index Terms- Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.

Abstract- We present a Switched-Current (SI) fourth-order bandpass Σ ∆ modulator IC prototype. It uses fully-differential circuits in 0.8µm CMOS technology to obtain a Dynamic Range (DR) larger than 55dB at 2.5MHz center frequency with 30kHz bandwidth − in accordance to the requirements of AM digital receivers. The prototype incorporates a single-ended to fully-differential current-mode buffer for testing purposes. The power consumption of the whole prototype (modulator plus buffer) is 60mW from a 5V supply voltage. 1