Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

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The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-on-a-chip based on core processors, while treating voltage (and correspondingly, the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial since changing the voltage by even a volt may take time equivalent to 100s to 10,000s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of non-linear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine real-life applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.

: Processors used in portable systems must provide highly energy-efficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The user-dependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known low-power techniques are re-evaluated against these metrics and in some cases are not found to be appropriate leading to a set of energy-efficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in lowenergy, high-performance design. 1. Introduction The recent explosive growth in portable electronics requires energy conscious design, without sacrificing performance. Simply increasing the battery capacity is not sufficient because the battery has become a significant fraction of the t...

The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrialstrength multimedia and communication applications.

This paper describes the design of a low-power microprocessor system that can run between 8Mhz at 1.1V and 100MHz at 3.3V. The ramifications of Dynamic Voltage Scaling, which allows the processor to dynamically alter its operating voltage at run-time, will be presented along with a description of the system design and an approach to benchmarking. In addition, a more in-depth discussion of the cache memory system will be given. 1. Introduction Our design goal is the implementation of a lowpower microprocessor for embedded systems. It is estimated that the processor will consume 1.8mW at 1.1V/ 8MHz and 220mW at 3.3V/100MHz using a 0.6 µm CMOS process. This paper discusses the system design, cache optimization, and the processor's Dynamic Voltage Scaling (DVS) ability. In CMOS design, the energy-per-operation is given by the equation where C is the switched capacitance and V is the operating voltage [2]. To minimize , we use aggressive low-power design techniques to reduce C and DVS to...

Low power design trends raise the possibility of using ambient energy to power future digital systems. A chip has been designed and tested to demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. A moving coil electromagnetic transducer was used as a power generator. Calculations show that power on the order of 400 W can be generated. The test chip integrates an ultra-low power controller to regulate the generator voltage using delay feedback techniques, and a low power subband filter DSP load circuit. Tests verify 500 kHz self-powered operation of the subband filter, a level of performance suitable for sensor applications. The entire system, including the DSP load, consumes 18 W of power. The chip is implemented in a standard 0.8 m CMOS process. A single generator excitation produced 23 ms of valid DSP operation at a 500 kHz clock frequency, corresponding to 11 700 cycles.

This versatile power converter controller provides dual outputs at a fixed switching frequency and can regulate either output voltage or target system delay (using an external -- filter). In the voltage regulation mode, the output voltage is monitored with an analog--digital (A/D) converter, and the feedback compensation network is implemented digitally. The generation of the pulsewidth modulation (PWM) signal is done with a hybrid delay line/counter approach, which saves power and area relative to previous implementations. Power devices are included on chip to create the two independently regulated output PWM signals. The key features of this design are its low-power dissipation, reconfigurability, use of either delay or voltage feedback, and multiple outputs.

An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A parasitic model of the buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4 % at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2 volts to 0.9 volts while supplying 9.5 amperes average current assuming an 80 nm CMOS technology. The area occupied by the buck converter is 12.6 mm 2. An analytic estimate of the efficiency is shown to be within 2.4 % of simulation at the target design point. Full integration of a high efficiency buck converter on the same die with a dual-VDD microprocessor is shown to be feasible. 1.

Abstract—This paper describes design and implementation of a digitally controlled DC-DC converter that provides a dynamically adjustable supply voltage for an RF power amplifier (RFPA). The techniques employed in the design include a combination of constant-frequency continuous conduction mode and a variablefrequency discontinuous conduction mode to achieve very high converter efficiency over a wide range of output power levels. The variable-frequency converter control is accomplished using a simple current-estimator circuit, which eliminates the need for current sensing. An FPGA-based digital controller implementation allows programmability of the mode transition and other controller parameters. In the complete experimental system, which consists of the digitally controlled DC-DC converter and a class-E RFPA operating at 10 GHz, experimental results show that the overall system efficiency is significantly improved over a wide range of RFPA output power levels, e.g. from 22 % to 65 % at a low power level. I.