. We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multiple-input floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2¯m double-poly p-well process through MOSIS. 1. Introduction Information processing using analog VLSI systems has recently become the subject of much interest and active research [1], [2]. In particular, the current-mode approach is the focus of much attention [3]. In this paradigm, the quantities of interest are represented by currents, whereas the circuit voltages are thought of as playing only an incidental role. Among the vast array of nonlinear operations required to perform current-mod...

¾¾ A 3-transistor nonvolatile analog storage cell with 14 bits effective resolution and railto -rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hotelectron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated. Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 µm n-well silicon BiCMOS process available from MOSIS. I. INTRODUCTION NE IMPEDIMENT to the development of silicon neural networks is the difficulty in storing analog weight values on-chip. Prior efforts typically used capacitive storage with clocked refresh [1], or multi-bit digital storage [2]. Both approaches pay a large penalty in terms of cell size, complexity, resolution,...

We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory -update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.

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We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated at subthres...

We describe a class of nonlinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call these circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element that produces an output current that is exponenial in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and we show experimental data from a squaring-reciprocal circuit breadboarded from bipolar-- floating-gate MOS (biFGMOS) MITEs that we fabricated in a 2--m double-poly CMOS process available through MOSIS. 1. PRODUCT-OF-POWER-LAW CIRCUITS Products, quotients, and power-law relationships figure prominently in many signal and information processing algorithms. Consequently, analog circuits embodying such relaionships are important components in the construction of analog VLSI information processing systems. In the Nonlinear Circuits Handbook from Analog Devices, we find the following clear description of a ...

this paper, the simplest to understand is the CAPS-and-DAC, whose basic architecture is shown in Fig. 1a. The voltage on any one capacitor is precisely set by a digital-to-analog converter (DAC) and de-multiplexer. Address lines select the memory location to be set, and data lines to the DAC encode the desired voltage. Since there are unavoidable leakage paths, the voltage of each memory must be refreshed periodically by using digitally encoded states, which are stored, typically, off-chip in conventional digital memory (SRAM or DRAM). The de-multiplexer circuitry would normally be integrated along with the capacitor array but the DAC could be located off chip to save space and reduce pin count. The rate of voltage decay due to charge leakage in CAPS-and-DAC memory depends on temperature, leakage pathway characteristics, and the capacity of each capacitor. The decay rate measured as a percentage of initial state is, to first order, independent of initial voltage. Therefore, to maintain state to a certain precision requires that refreshing occurs frequently enough to keep the associated voltage ripple, expressed as a binary fraction of the full scale swing, less than 0.5 of a least significant bit (LSB). If we assume the decay is a single exponential then the refresh frequency 3

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectiviy for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current. I. Introduction There are five requirements for a learning synapse [1]. First, the weight should be stored permanently in the absence of learning. Second, the synapse must compute as a...

We have designed and fabricated a VLSI synapse that can learn a conditional probability or correlation between spike-based inputs and feedback signals. The synapse is low power, compact, provides nonvolatile weight storage, and can perform simultaneous multiplication and adaptation. We can calibrate arrays of synapses to ensure uniform adaptation characteristics. Finally, adaptation in our synapse does not necessarily depend on the signals used for computation.

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines.