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26
Fast Module Mapping and Placement for Datapaths in FPGAs
 In ACM/SIGDA International Symposium on Field Programmable Gate Arrays
, 1998
"... By tailoring a compiler treeparsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure; this allows exploitation of specialized datapath features in FPGAs, ret ..."
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Cited by 44 (2 self)
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By tailoring a compiler treeparsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure; this allows exploitation of specialized datapath features in FPGAs, retains regularity, and also results in a smaller problem size. To further achieve high mapping speed, we formulate the problem as tree covering and solve it efficiently with a lineartime dynamic programming algorithm. In a novel extension to the treecovering algorithm, we perform module placement simultaneously with the mapping, still in linear time. Integrating placement has the potential to increase the quality of the result since we can optimize total delay including routing delays. To our knowledge this is the first effort to leverage a grammarbased tree covering tool for datapath module mapping. Further, it is the first work to integrate simultaneous placement with module mapping in a w...
Efficient retargetable code generation using bottomup tree pattern matching
 Computer Languages
, 1990
"... Abstract Instruction selection is the primary task in automatic code generation. This paper proposes a practical system for performing optimal instruction selection based on tree pattern matching for expression trees. A significant feature of the system is its ability to perform code generation with ..."
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Cited by 33 (0 self)
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Abstract Instruction selection is the primary task in automatic code generation. This paper proposes a practical system for performing optimal instruction selection based on tree pattern matching for expression trees. A significant feature of the system is its ability to perform code generation without requiring cost analysis at code generation time. The target machine instructions are specified as attributed production rules in a regular tree grammar augmented with cost information in Graham Glanville style. Instruction selection is modelled as a process of determining minimum cost derivation for a given expression tree. A matching automaton is used for instruction selection. Cost information is encoded into the states of this automaton so that cost analysis is not required at code generation time. The folding technique of table compression is extended to this automaton and two schemes of table compression based on cost information are proposed. Compilers Retargetable code generation Codegenerator Codegeneratorgenerator Treepattern matching Instruction selection Table compression
Automatic Compilation of C for Hybrid Reconfigurable Architectures
 UNIVERSITY OF CALIFORNIA BERKELEY
, 2002
"... ..."
Construction of Verified Software Systems with ProgramChecking: An Application To Compiler BackEnds
, 1999
"... This paper describes how programchecking can be used to significantly reduce the amount of verification work to establish the implementation correctness of software systems which may be partly generated by unverified construction tools. We show the practicability of our approach with an application ..."
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Cited by 7 (2 self)
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This paper describes how programchecking can be used to significantly reduce the amount of verification work to establish the implementation correctness of software systems which may be partly generated by unverified construction tools. We show the practicability of our approach with an application to the construction of verified compiler backends. The basic idea of programchecking is to use an unverified algorithm whose results are checked by a verified component at run time. RunTime Result Verification in our approach assures formal correctness of the software system and its implementation if partial correctness of the application is sufficient. In our example the approach does not only simplify the construction of verified compilers because checking the result of the transformations is much simpler to verify than the verification of an optimizing code selection. Furthermore, we are still able to use existing compiler generator tools without modifications. Compiler verification plays two roles in this paper: First it closes the gap between verification on highlevel programming language and the implementation on machine level using a verified compiler to translate the verified program to machine code. Second it serves as a largescale case study for software verification. This work points out the tasks which still have to be verified and it discusses the flexibility of the approach.
Technology Mapping for LookupTable Based FieldProgrammable Gate Arrays
, 1992
"... Field Programmable Gate Arrays (FPGAs) provide a new approach to Application Speci c Integrated Circuit (ASIC) implementation that features both large scale integration and user programmability. The logic capacity of these devices is large enough to make automated synthesis essential for the e cient ..."
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Cited by 7 (0 self)
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Field Programmable Gate Arrays (FPGAs) provide a new approach to Application Speci c Integrated Circuit (ASIC) implementation that features both large scale integration and user programmability. The logic capacity of these devices is large enough to make automated synthesis essential for the e cient design of FPGA circuits. This thesis focuses on the class of FPGAs that use lookup tables (LUTs) to implement combinational logic. A Kinput lookup table is a digital memory that can implement anyBoolean function of K variables. Lookup table circuits present new challenges for logic synthesis, particularly technology mapping, which is the phase of logic synthesis directly concerned with the selection of the circuit elements to implement the nal circuit. Conventional librarybased technology mapping has di culty with lookup table circuits because each lookup table can implement a large number of di erent functions. This thesis presents two new technology mapping algorithms that construct circuits of Kinput lookup tables from networks of ANDs, ORs and NOTs. The rst algorithm, referred to as the area algorithm, minimizes the number of LUTs in the
A New Algorithm for Linear Regular Tree Pattern Matching
 Theoretical Computer Science
, 1998
"... ..."
Code Generation Techniques
 In INFOCOM (1
, 1992
"... Optimal instruction scheduling and register allocation are NPcomplete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayedload architectures to expression trees we are able to find optimal schedules quickly. This thesis ..."
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Cited by 5 (0 self)
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Optimal instruction scheduling and register allocation are NPcomplete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayedload architectures to expression trees we are able to find optimal schedules quickly. This thesis presents a fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. In addition, the algorithm is simple
Tree Pattern Matching for ML (Extended Abstract)
, 1985
"... This paper addresses the problem of compiling such sequences of patterns into efficient patternmatching code. The goal is to minimize the number of tests or discriminations that have to be applied to any given argument to determine the first pattern it matches. Our approach is to transform a sequen ..."
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Cited by 5 (0 self)
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This paper addresses the problem of compiling such sequences of patterns into efficient patternmatching code. The goal is to minimize the number of tests or discriminations that have to be applied to any given argument to determine the first pattern it matches. Our approach is to transform a sequence of patterns into a decision tree, i.e. a tree which encodes the patterns and defines the order in which subterms of any given value term have to be tested at runtime to determine which pattern matches the value. Each internal node of a decision tree corresponds to a matching test and each branch is labeled with one of the possible results of the matching test and with a list of the patterns which remain potential candidates in that case. It is then straightforward to translate the decision tree into code for pattern matching. During the construction of a decision tree it is also easy to determine whether the pattern set is "exhaustive", meaning every possible argument value matches at least one pattern, and whether there are any "redundant" patterns (i.e. patterns that are matched only by values that are already matched by an earlier pattern). Nonexhaustive definitions and redundant patterns are anomalies that can be  2  usefully reported by the compiler. Our goal in constructing the decision tree is simply to minimize the total number of testnodes. This minimizes the size of the generated code and also generally minimizes the number of tests performed on value terms. However, we have discovered that finding the decision tree with the minimum number of nodes is an NPcomplete problem. This result is established by reduction from one of the trie index construction problems (pruned Otrie space minimization), which was proved to be NPcomplete in [Co76, CS77]. Therefore...
Declarative Peephole Optimization Using String Pattern Matching
, 1999
"... Peephole optimisation as a last step of a compilation sequence capitalises on significant opportunities for removing low level code slackness left over by the code generation process. We have designed a peephole optimiser that operates using a declarative specification of the optimisations to be per ..."
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Cited by 4 (0 self)
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Peephole optimisation as a last step of a compilation sequence capitalises on significant opportunities for removing low level code slackness left over by the code generation process. We have designed a peephole optimiser that operates using a declarative specification of the optimisations to be performed. The optimiser's implementation is based on string pattern matching using regular expressions. We used this approach to prototype an optimiser to convert target machine instruction sequences containing conditional execution of instructions inside loop bodies into code that adaptively executes the optimum branch instructions according to the program's branch behaviour. Keywords Peephole optimization; branch prediction; regular expressions. 1 Introduction Peephole optimisation [ASU85, p. 554558] as a last step of a compilation sequence capitalises on significant opportunities for removing low level code slackness left over by the code generation process. In addition, as peephole o...