This paper gives an overview of methods used for Design Space Exploration (DSE) at the system- and micro-architecture levels. The DSE problem is considered to be two orthogonal issues: (I) How could a single design point be evaluated, (II) how could the design space be covered during the exploration process? The latter question arises since an exhaustive exploration of the design space by evaluating every possible design point is usually prohibitive due to the sheer size of the design space. We therefore reveal trade-o#s linked to the choice of appropriate evaluation and coverage methods. The designer has to balance the following issues: the accuracy of the evaluation, the time it takes to evaluate one design point (including the implementation of the evaluation model), the precision/granularity of the design space coverage, and last but not least the possibilities for automating the exploration process. We also list common representations of the design space and compare current system and micro-architecture level design frameworks. This review thus eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work. It is focused on System-on-a-Chip designs, particularly those used for network processors. These systems are heterogeneous in nature using multiple computation, communication, memory, and peripheral resources.

Traditionally, in the field of embedded systems low power consumption and low cost have been always regarded as stringent specification constraints. In recent years, high computational power has become a fundamental requirement as well. This has been mainly determined by the introduction of new features, typical of general-purpose systems, e.g. GUI-based interfaces. In this setting, low cost, low power consumption, significant computational power and short time-to-market are conflicting needs that have to be accommodated. The adoption of a simple multiprocessor on a single chip can be deemed a convenient answer, because it is able to deliver a considerable computing power using low-cost and low-power CPU cores. In this paper, we take into account SPP, a cartographic system to be deployed on hand-held devices. We present the overall methodology used for designing the multiprocessor architecture of its hardware platform, and we focus on the activities that have been carried out to get to the more convenient setting for the system, respect to the specification requirements. The adopted design process includes two phases. The former (coarse-grain exploration) is aimed at selecting an architecture suitable to properly support the appliance features; the latter (finegrain exploration) is aimed at tuning the parameter values with the purpose of obtaining to the best system setting. We show how this tuning phase for the SPP chipset has involved the selection of the clock rate and the cache coherence strategy, and the analysis of bus traffic. Moreover, from the discussed study it becomes evident that further improvements in the system performance have to be pursued possibly operating on the software components.

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Abstract — We propose a methodology for the early estimation of communication implementation choices effects, starting from an abstract transaction level system model (TLM). The reference version of TLM considered is the OSCI library. The methodology is based on the computation of metrics that abstract useful information from the initial system model. The metrics are precisely defined upon a general, formal model of transaction level system descriptions. A set of design problems of relevant interest, such as shared communication resources assignment, pipelining partitioning, bandwidth and latency constraints estimation, is considered to show some potential applications of the metrics proposed. The first assumption is the conceptual basis for the abstract communication synthesis approaches. The second assumption implies that it is possible, starting from a purely functional description, to compare different implementation choices without having to directly refine a model or to generate a prototype. The information extracted from the analysis of the abstract system model could be exploited to guide architectural choices to determine the number and type of resources to employ. Furthermore, such information can drive the automatic synthesis of parts of the system, to drive automatic algorithms in achieving optimal or satisfying results (such as, for instance, various types of resource sharing). I.