Systems-on-C hip (SoC) are evol ing toward complm heterogeneous mul tiprocessors made of many predesigned macrocelV or subsystems with appl$22 ion-specific interconnections. Intra-chip interconnects are thus becoming one of the central elV' ts of SoC design and pose conflicting goal in terms of l w energy per transmitted bit,guaranteed signal integrity,and ease of design. This work introduces and shows first resul ts on a novel interconnect system which uses l w-swing signal$' g,error detection codes, and a retransmission scheme; it minimises the interconnect vol tage swing and frequency subject to workl oad requirements and S/N conditions. Simul ation resul ts show that tangib l savings in energy can be attained wh il achieving at the same time more robustness tol arge variations in actual workl,V ,noise,and technol$' qual$ y (al quantities easil mispredicted in very complm systems and advanced technol ogies). It can be argued that traditional worst-case correct-by-design paradigmwil bel$V andl ess appl#O2 l in future mu l ibil$#P transistor SoC and deep sub-micron technol ogies; this work represents a first exampl e towards robust adaptive designs.

In modern embedded systems including communication and multimedia applications, large frac-tion of power is consumed during memory access and data transfer. Thus, buses should be de-signed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address bus ordering problems for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30 % to 46.7 % depending on capacitance components can be obtained without any circuit overhead. 1

The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are needed for deep-submicron buses. One such coding technique uses the simple observation that coupling capacitances are always charged and discharged by activity on neighboring bus lines, where one line has an odd number and the other has an even number (if bus lines are numbered “in-order”). We thus propose to reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, the Odd Invert, and Even Invert line, respectively. We obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to transmit on the bus. Even after encoding, the coupling activity for a pair of bus lines is still strongly dependent on the data. In particular the toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events. We thus propose a targeted Two-Phase transfer in order to reduce total power only on the pairs of lines that carry such toggling events.

Abstract—Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity—in spite of the decreased signal to noise ratio—by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements. Index Terms—Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology. I.

In modern digital circuits the total power attributed to wires is increasing. Reducing the power consumption in wires play a major role in low power design. Coupling transitions contribute to significant energy loss in deep sub-micron buses. Earlier schemes using the switching activity minimization based upon the substrate capacitances are not valid in these buses. Hence, a new low energy bus-encoding scheme is proposed which showed 10 % reduction in coupling transitions for 8 and 16 bit data.

In this paper we present a comprehensive mathematical analysis of the energy dissipated in deep sub-micron (DSM) buses. The estimation is based on an elaborate bus model that includes all the distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a compact closed form. The notion of activity of individual lines is generalized to that of the activity matrix of the bus. The activity matrix is used for statistical estimation of the power dissipation in DSM buses.

In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between inter-wire capacitance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model. Using this representation we propose a coding scheme without memory which reduces energy dissipation in the bus model by approximately 20-30 % compared to an uncoded system. At the same time the proposed coding scheme is easy to realize, in terms of standard cells needed, compared to several previously proposed solutions.

Keywords: Bus interface design, Low-power bus encoding This deliverable evaluates the applicability of encoding techniques in the context of the design of low-power communication buses. The existing literature is reviewed in detail with the purpose of identifying the classes of bus encoding schemes that are most suitable to the EASY project, namely, those which are applicable in the context of the HIPERLAN/2 SoC development. Several algorithms have been implemented to allow a meaningful comparison of different encoding methods, and thus enable a first screening of the techniques that could then be applied during the HIPERLAN/2 SoC development. Copyright © 2002 ICOM POLITO

Abstract — Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. It not only reduces datapath unit power consumption in the resultant registertransfer level (RTL) architecture, but also optimizes interconnects for power. We take into account physical design information and coupling capacitance to estimate interconnect power consumption accurately for deep sub-micron (DSM) technologies. We show that there is significant spurious (i.e., unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared with interconnect-unaware power-optimized circuits, interconnect power can be reduced by 53.1 % on an average, while overall power is reduced by an average of 26.8 % with negligible area overhead. Compared with area-optimized circuits, the interconnect power reduction is 72.9 % and overall power reduction is 56.0 % with 44.4 % area overhead. The power reductions are obtained solely through switched capacitance reduction (no voltage scaling is assumed). Index Terms — High-level synthesis, Interconnect, Low power.

With decreasing feature size on silicon, the coupling capacitances of buses grow rapidly causing a significant impact on the power consumption of the whole chip. Thus, buses should be designed and optimized to dissipate less power without sacrificing performance. In this paper, we address this problem by simultaneously optimizing wire permutation, inversion and spacing (space between consecutive wires) using a combination of optimal as well as genetic algorithms. Unlike previous studies, our approach is applicable to not only address buses (behave more regularly), but also instruction buses of microprocessors. For the spacing problem, an algorithm is presented which determines the optimal solution instead of applying time consuming heuristic algorithms as presented in [10]. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. We simulate different combinations among permutation, spacing, and inversion. Integrated all optimization techniques together, our approach can save energy up to 68 % for the best case and 58 % on average while only increasing the total wire space by about 50 % (compared to a bus with minimal spacing between adjacent wires for a particular technology). 1.