Abstract — We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. Many nanotechnologies, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron tunneling (SET), are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionally-correct threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, upto 80.0 % and 70.6 % reduction in gate count and interconnect count, respectively, is possible with the average being 22.7 % and 12.6%, respectively. Furthermore, the synthesized networks are well-balanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multi-level threshold logic design. Index Terms — Design automation, logic synthesis, QCA, RTD, threshold networks.

Resonant tunneling transistors and circuit architectures with enhanced computational functionality are promising candidates for future nano-scale integration. In this paper we propose a full adder cell based on multiple terminal linear threshold gates. The threshold gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field effect transistors. Together with a bit-level pipelining scheme this leads to an efficient implementation with a minimal logic depth of two circuit layers. 1 Introduction During the last decades the progress in microelectronics primarily results from the scaling of the devices and the development of circuit families such as ECL, NMOS, and CMOS. Today, originating from the possibility to fabricate semiconductor heterostructures with atomic layer thickness, there are tremendous activities in research and development of devices so small that quantum mechanical effects become relevant for their operation. Among the devices bein...

We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on the development of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multi-output benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77% reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, the synthesized networks are well-balanced, and hence delay-optimized.

This paper analyzes the impact of nano-scale technology on future circuit design and describes several prototypes of logic and memory applications. Resonant tunneling transistors, single electron transistors, and quantum cellular automata are reviewed as relevant nanoelectronic device categories. In regard to the limited interconnectivity and the sensitivity of the devices to parameter variations we discuss bit level systolic arrays, a propagate instruction array processor, and fault tolerant logic. Furthermore, functional integration, that is the possibility of exploiting quantum effects to obtain a function specific behavior, is illustrated as design technique by compact memory cells and logic families with reduced circuit complexity.

This paper describes the design of depth-2 parallel counters with a novel circuit architecture basing on quantum-effect devices. The elementary components of the counters are linear threshold gates with fixed integer weights. To obtain a compact implementation each threshold gate consists of two serially connected resonant tunneling diodes which are integrated in a hybrid way together with multiple heterostructure field effect transistors. A potential application is the computation of arithmetic functions with a reduced logic depth in high performance digital signal processing systems.

This report is a summary of the activities in the field of resonant tunneling device circuit design. The presented work has been performed by the Department of Microelectronics of the University of Dortmund (UNIDO) and the Solid-State Electronics Department of the Gerhard-Mercator University of Duisburg (GMUD) during the first year of the Microelectronics Advanced Research Initiative projects ANSWERS (Autonomous Nanoelectronic Systems with Extended Replication and Signalling) and LOCOM (Logic Circuits with Reduced Complexity based on Devices with Higher Functionality). As part of the ANSWERS work-package the principal task of UNIDO is to investigate novel logic circuit architectures for resonant tunneling devices, to perform circuit simulations, and to specify the electrical device parameters. The basic device configuration is a monolithically integrated resonant tunneling diode heterostructure field-effect transistor (RTD-HFET). This device and the demonstrator circuits are fabricated by the LOCOM partner GMUD.

This paper describes the design of arithmetic circuits based on hybrid integratedresonant tunneling diodes and heterostructure #eld-e#ect transistors. The key components are depth-2 parallel counters consisting of multiple terminal threshold gates. In particular, we propose a novel parallel addition scheme by combining threshold logic and systolic VLSI-algorithms for bit-level computations. The approach is motivatedby the demand for locally interconnected circuit modules to solve the wiring problem in nanoelectronic circuits. 1 Introduction During the last decades the progress in microelectronics primarily results from the scaling of the devices and the development of information processing systems such as microprocessors and memories. Today, originating from the possibility to fabricate semiconductor heterostructures with atomic layer thickness, there are tremendous activities in research and developmentof devices so small that quantum mechanical e#ects become relevant for their op...