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A Fast New DES Implementation in Software
, 1997
"... . In this paper we describe a fast new DES implementation. This implementation is about five times faster than the fastest known DES implementation on a (64bit) Alpha computer, and about three times faster than than our new optimized DES implementation on 64bit computers. This implementation uses ..."
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. In this paper we describe a fast new DES implementation. This implementation is about five times faster than the fastest known DES implementation on a (64bit) Alpha computer, and about three times faster than than our new optimized DES implementation on 64bit computers. This implementation uses a nonstandard representation, and view the processor as a SIMD computer, i.e., as 64 parallel onebit processors computing the same instruction. We also discuss the application of this implementation to other ciphers. We describe a new optimized standard implementation of DES on 64bit processors, which is about twice faster than the fastest known standard DES implementation on the same processor. Our implementations can also be used for fast exhaustive search in software, which can find a key in only a few days or a few weeks on existing parallel computers and computer networks. 1 Introduction In this paper we describe a new implementation of DES[4], which can be very efficiently executed ...
FOX: a New Family of Block Ciphers
 Selected Areas in CryptographySAC 2004,LNCS 2595
, 2004
"... In this paper, we describe the design of a new family of block cipher, named FOX and designed upon the request of MediaCrypt AG [23]. The main features ofthis design, besides a very high security level, are a large flexibility in terms of use ..."
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Cited by 25 (3 self)
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In this paper, we describe the design of a new family of block cipher, named FOX and designed upon the request of MediaCrypt AG [23]. The main features ofthis design, besides a very high security level, are a large flexibility in terms of use
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
"... Abstract—With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent confidentially over the network without fear of hackers or unauthorized access to it. This makes security implemen ..."
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Abstract—With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent confidentially over the network without fear of hackers or unauthorized access to it. This makes security implementation in networks a crucial demand. Symmetric Encryption Cores provide data protection via the use of secret key only known to the encryption and decryption ends of the communication path. In this paper, first, an overview of two well known symmetric encryption cores is presented, namely the 3DES and RC5. Then a performance evaluation of their computer based implementation is compared to demonstrate the RC5 superior performance. The conventional hardware architecture of the RC5 core is presented and investigated. A hardware system design is proposed to improve its performance. The proposed architecture achieved with three stage pipeline technique an increased encryption throughput as compared to related work. By exploiting modern features in Field Programmable Gate Arrays (FPGA), which allow the modeling of a SystemonProgrammableChip (SoPC), this paper proposes a model for symmetric encryption algorithms (e.g., RC5). Structural System analysis of the proposed model shows that it offers extra security against singlesite physical access attack that other implementations are vulnerable to. By evaluating the performance of this proposed SoPC model, one finds that it raises the encryption throughput to 300 Mbps. Hence, we report over 80 % increase in the encryption throughput as compared to related work. Moreover, our work lowers the implementation cost due to the integration of all system parts into one chip. Index Terms—Cryptography, SystemsonProgrammable Chips, analysis and simulation, Hardware Description Language I.
Differential Cryptanalysis of DES
, 2000
"... this paper we will describe DES and briefly present TDEA. Furthermore, we will describe an attack (differential cryptanalysis) that can be applied not only to DES but to many DESlike iterated cryptosystems (such as Lucifer, FEAL [12] and GDES [11]). This is a chosen plaintext attack which uses only ..."
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this paper we will describe DES and briefly present TDEA. Furthermore, we will describe an attack (differential cryptanalysis) that can be applied not only to DES but to many DESlike iterated cryptosystems (such as Lucifer, FEAL [12] and GDES [11]). This is a chosen plaintext attack which uses only the resultant ciphertexts. The basic tool of the attack is the ciphertext pair: a pair of ciphertexts whose plaintexts have particular differences (thus the name differential). The two plaintexts can be chosen at random, as long as they satisfy the difference condition, and the cryptanalyst does not have to know their values. The attack is statistical in nature and can fail in rare instances.
Fast Software Implementations of Block Ciphers
, 1998
"... Three block ciphers are considered to determine how well they can be implemented on existing superscalar architectures such as the Intel Pentium. An examination of the Pentium architecture suggests that substantial performance increases can be achieved if particular rules are followed. Software libr ..."
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Three block ciphers are considered to determine how well they can be implemented on existing superscalar architectures such as the Intel Pentium. An examination of the Pentium architecture suggests that substantial performance increases can be achieved if particular rules are followed. Software libraries are written in highlevel C language and lowlevel assembly language to produce a package of routines which achieve a near optimal performance level on a current processor architecture. The structure of each algorithm is studied to determine if it is possible to alternatively implement the algorithm such that certain steps are reordered or reduced. Using the Intel MMX architectural advances it is observed that one algorithm benefits dramatically from a new implementation that takes advantage of MMX strengths. © Copyright by Julian B. Sessions
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"... this paper we are interested in characteristics for which the probability that a random pair is a right pair varies between different keys. We call these characteristics conditional characteristics ..."
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this paper we are interested in characteristics for which the probability that a random pair is a right pair varies between different keys. We call these characteristics conditional characteristics