We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory -update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.

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We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated at subthres...

The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still not well understood. This paper highlights the challenges to current test methodologies arising from technology driven trends, and will present an overview of emerging techniques that address deep submicron test challenges. 1.

We have studied the performance of a CCD tracker using minimum ionizing particles (MIP's) from KEK PS beam line. The detector consists of three layers of CCD sensors manufactured by Hamamatsu Photonics, which suppress the dark current at surface by one order of magnitude compared with that of the conventional ones. We have observed MIP's can be detected with su#cient signal to noise ratio even up to +5 # C. The position resolution as well as the detection e#ciency of this detector are also given. 1 Introduction Vertex detectors will play a crucial role to investigate TeV physics at future linear colliders [1]. CCD (Charge Coupled Device) is one of the best candidates for this application because of its unambiguous reconstruction capability (2 dimensional pixels), less occupancy (large granularity) and less multiple scattering (thin detector)) [2]. For future linear collider application, we have been studying properties of CCD at room temperature in order to achieve a compact #...

Optical microsystems based on silicon technology have been studied in this work. Components applying integrated optical structures and microelectromechanical systems (MEMS) have been developed. New functionality, lower component costs, and improved reliability have been aimed at by the integration and miniaturization of the novel concepts. The four components studied in this work represent new ideas based on well established material technologies and manufacturing schemes. The first three components are based silicon integrated optics and the fourth component is based on silicon micromechanics. A novel architecture for a surface plasmon resonance (SPR) sensor based on a silicon nitride slab waveguide structure was proposed and studied. Industrial aspects and feasibility for the practical sensor design of the introduced concept were considered. As a main result a proof-of-concept was shown by demonstrating the device sensitivity to humidity. A surface plasmon sensor fabricated with a silicon nitride waveguide technology has applications as a chemical and biochemical sensor.

Abstract—The gate current of MOS tunneling diodes biased at inversion region with different substrate doping is investigated. For p-type substrate (1–5-cm) devices, the tunneling diode works in the deep depletion region and the inversion current is dominated by the thermal generation rate of minority electrons via traps at Si/SiOP interface and in the deep depletion region. The activation energy is approximately equal to half of the silicon bandgap independent of gate voltage. For devices on p C substrate (0.01–0.05-cm), the band-to-traps tunneling and band-to-band tunneling are the dominating current components at inversion bias, and reveal a strong field dependence and a weak temperature dependence. The band-to-traps and band-to-band current components are even more significant in the devices on the p CC substrate (0.001–0.0025-cm). Finally, the effects of temperature and light illumination on inversion current of MOS tunneling diodes will be also discussed. Index Terms—Inversion current, MOS tunneling diode, ultrathin oxide. I.

In this work, we derived the new diffusion model combining the atomistic theory of diffusion and the vacancy point defect mechanism. A ion migration model was developed [PJ92] to better characterize the diffusion of substitutional impurities with the vacancy point defect mechanism in silicon. Antimony, Sb, was used as the dopants, the best candidate for giving ultrashallow n + /p junctions (below 100 nm) in ultralarge-scale integration (ULSI) technology [SHSW85,SHH86]. Unlike earlier equations, factors such as the effects of electric field, the Gibbs free energy of migration, Debye frequency, and oxidation retarded diffusion were considered in describing the movement of charged impurities in silicon lattice. This new ionmigration model was then being tested numerically with the experimental data obtained from Nobili [NAA + 89]. The carrier concentration profiles generated from this new ion-migration model matches well with the experimental profiles for the cases of 1 hour and 4 hou...

Simulation results on a novel extended p dual source SOI MOSFET are reported. It is shown that the presence of the extended p region on the source side, which can be fabricated using the post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's.

The demands of future CMOS devices require a new gate dielectric material with higher dielectric constant than SiO 2 . Aluminum oxide is one of the high-k materials and an interesting candidate.