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Incorporating Efficient Assertion Checkers into Hardware Emulation
 IEEE Intl. Conference on Computer Design (ICCD’05
, 2005
"... Assertion–based verification (ABV) is emerging as a paramount technique for industrial–strength hardware verification, especially through the emerging Property Specification Language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardw ..."
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Assertion–based verification (ABV) is emerging as a paramount technique for industrial–strength hardware verification, especially through the emerging Property Specification Language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardware emulation capable of supporting ABV. We develop a tool that generates hardware assertion checkers for inclusion into efficient circuit emulation. The MBAC checker generator is outlined, together with the algorithms for optimized assertion–circuit generation. Experiments show that MBAC outperforms the best known checker–generator. 1.
Efficient execution in an automated reasoning environment
 Journal of Functional Programming
, 2006
"... Abstract We describe a method to permit the user of a mathematical logic to write elegant logical definitions while allowing sound and efficient execution. We focus on the ACL2 logic and automated reasoning environment. ACL2 is used by industrial researchers to describe microprocessor designs and ot ..."
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Abstract We describe a method to permit the user of a mathematical logic to write elegant logical definitions while allowing sound and efficient execution. We focus on the ACL2 logic and automated reasoning environment. ACL2 is used by industrial researchers to describe microprocessor designs and other complicated digital systems. Properties of the designs can be formally established with the theorem prover. But because ACL2 is also a functional programming language, the formal models can be executed as simulation engines. We implement features that afford these dual applications, namely formal proof and execution on industrial test suites. In particular, the features allow the user to install, in a logically sound way, alternative executable counterparts for logicallydefined functions. These alternatives are often much more efficient than the logically equivalent terms they replace. We discuss several applications of these features. 1 Introduction This paper is about a way to permit the functional programmer to prove efficientprograms correct. The idea is to allow the provision of two definitions of the program: an elegant definition that supports effective reasoning by a mechanizedtheorem prover, and an efficient definition for evaluation. A bridge of this sort,
An Operational Semantics for Weak PSL
 Formal Methods in ComputerAided Design, LNCS 3312
, 2004
"... Extending linear temporal logic by adding regular expressions increases its expressiveness. However, as for example, problems in recent versions of Accellera’s Property Specification Language (PSL) as well as in OpenVera’s ForSpec and other property languages show, it is a nontrivial task to give a ..."
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Extending linear temporal logic by adding regular expressions increases its expressiveness. However, as for example, problems in recent versions of Accellera’s Property Specification Language (PSL) as well as in OpenVera’s ForSpec and other property languages show, it is a nontrivial task to give a formal denotational semantics with desirable properties to the resulting logic. In this paper, we argue that specifying an operational semantics may be helpful in guiding this work, and as a bonus leads to an implementation of the logic for free. We give a concrete operational semantics for Weak PSL, which is the safety property subset of PSL. We also propose a denotational semantics which we show to be equivalent to the operational one. This semantics is inspired by a new denotational semantics proposed in recent related work.
Formal verification of synchronizers
 In CHARME 2005
, 2005
"... Abstract. Large Systems on Chips (SoC) comprise multiple clock domains, and interdomain data transfers require synchronization. Synchronizers may fail due to metastability, but when using proper synchronization circuits the probability of such failures can be made negligible. Failures due to unexpe ..."
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Abstract. Large Systems on Chips (SoC) comprise multiple clock domains, and interdomain data transfers require synchronization. Synchronizers may fail due to metastability, but when using proper synchronization circuits the probability of such failures can be made negligible. Failures due to unexpected order of events (caused by interfacing multiple unrelated clocks) are more common. Correct synchronization is independent of event order, and can be verified by model checking. Given a synchronizer, a correct protocol is guessed, verification rules are generated out of the protocol specification, and the model checker applies these rules to the given synchronizer. An alternative method verifies correct data transfer and seeks potential data missing or duplication. Both approaches require specific modeling of multiple clocks, allowing for nondeterminism in their relative ordering. These methods have been applied successfully to a twoflipflop synchronizer and a dual clock FIFO. 1
Z.; “Proving and disproving assertion rewrite rules with automated theorem provers”, HLDVT '08
 IEEE International
, 2008
"... Abstract — Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant dif ..."
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Abstract — Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, workable procedures for proving the correctness of these rules must be established. In this paper, we outline the methodology for computerassisted proofs of a set of previously published rewrite rules for PSL properties. We show how to express PSL’s syntax and semantics in the PVS theorem prover, and proceed to prove the correctness of a set of thirty rewrite rules. In doing so, we also demonstrate how to circumvent issues with PSL semantics regarding the never and eventually! operators. I.
Constructing checkers from PSL properties
 In Proc. 15th Int’l Conf. on Control Systems and Computer Science
, 2005
"... Abstract: Model checking and simulation are the main techniques widely used in hardware verification. The past years trend is to bring together these two verification techniques in order to employ knowledge and tools produced by one to help the other. This paper describes a tool that translates prop ..."
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Abstract: Model checking and simulation are the main techniques widely used in hardware verification. The past years trend is to bring together these two verification techniques in order to employ knowledge and tools produced by one to help the other. This paper describes a tool that translates properties written in PSL, a model checking language, into checkers written in languages suitable for simulation. The tool has two main focuses: first, retargetability, and second, simplicity, efficiency and clarity of the resulted checkers. However, its speed is in the same order of magnitude with those of commercial tools already existing on the market.
Embedding and Verification of PSL using AsmL
"... Abstract. In this paper, we propose a methodology to integrate the Property Specification Language (PSL) in the verification process of systems designed using Abstract States Machines (ASMs). We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL propertie ..."
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Abstract. In this paper, we propose a methodology to integrate the Property Specification Language (PSL) in the verification process of systems designed using Abstract States Machines (ASMs). We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL properties as part of the design. For the verification, we propose a technique based on the AsmL tool that translates the code containing both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage of the AsmL language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C # code and an FSM representation from an AsmL model. We applied our approach on SystemC designs, which are translated into AsmL models. Experimental results on a bus structure case study provided in the SystemC library showed a superiority of our approach to conventional verification. 1
PSL semantics in higher order logic
"... In a paper, published in the journal Formal Aspects of Computing (FAC) [Gor03] 1, we described a deep semantic embedding of Version 1.01 of the Accellera Property Specification Language (PSL) in higher order logic. The main goal of that paper was to demonstrate that mechanised theorem proving can be ..."
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In a paper, published in the journal Formal Aspects of Computing (FAC) [Gor03] 1, we described a deep semantic embedding of Version 1.01 of the Accellera Property Specification Language (PSL) in higher order logic. The main goal of that paper was to demonstrate that mechanised theorem proving can be a useful aid to the validation of the semantics of an industrial design language.
A Satellite Event of the ETAPS 2004 group of conferences Participants ’ Proceedings
, 2004
"... This volume contains material provided by the speakers to accompany their presentations at ..."
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This volume contains material provided by the speakers to accompany their presentations at