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29
BorderBlock Triangular Form and Conjunction Schedule in Image Computation
 in Formal Methods in ComputerAided Design
, 2000
"... . Conjunction scheduling in image computation consists of clustering the parts of a transition relation and ordering the clusters, so that the size of the BDDs for the intermediate results of image computation stay small. We present an approach based on the analysis and permutation of the depende ..."
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Cited by 38 (6 self)
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. Conjunction scheduling in image computation consists of clustering the parts of a transition relation and ordering the clusters, so that the size of the BDDs for the intermediate results of image computation stay small. We present an approach based on the analysis and permutation of the dependence matrix of the transition relation. Our algorithm computes a borderedblock lower triangular form of the matrix that heuristically minimized the active lifetime of variables, that is, the number of conjunctions in which the variables participate. The ordering procedure guides a clustering algorithm based on the affinity of the transition relation parts. The ordering procedure is then applied again to define the cluster conjunction schedule. Our experimental results show the effectiveness of the new algorithm. 1 Introduction Symbolic algorithms for model checking [11] spend most of the time computing the predecessors or successors of sets of states. The algorithms for these image ...
Checking equivalence for partial implementations
 UNIVERSITY OF COLORADO AT BOULDER
, 2001
"... We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which a ..."
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Cited by 32 (12 self)
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We consider the problem of checking whether a partial implementation can (still) beextended to a complete design which is equivalent to a given full specification. Several algorithms trading off accuracy and computational resources are presented:Starting with a simple 0,1,Xbased simulation, which allows approximate solutions, but is not able to find all errors in the partial implementation, we consider more and more exactmethods finally covering all errors detectable in the partial implementation. The exact algorithm reports no error if and only if the current partial implementation conforms tothe specification, i.e. it can be extended to a full implementation which is equivalent to the specification.We give a series of experimental results demonstrating the effectiveness and feasibility of the methods presented.
SATbased Image Computation with Application in Reachability Analysis
 Proc. FMCAD
, 2000
"... Abstract. Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential test. Existing BDDbased symbolic algorithms for image computation are limited by memory resources in practic ..."
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Cited by 27 (4 self)
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Abstract. Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential test. Existing BDDbased symbolic algorithms for image computation are limited by memory resources in practice, while SATbased algorithms that can obtain the image byenumerating satisfying assignments to a CNF representation of the Boolean relation are potentially limited by time resources. We propose new algorithms that combine BDDs and SAT inorder to exploit their complementary bene ts, and to o er a mechanism for trading o space vs. time. In particular, (1) our integrated algorithm uses BDDs to represent the input and image sets, and a CNF formula to represent the Boolean relation, (2) a fundamental enhancement called BDD Bounding is used whereby the SAT solver uses the BDDs for the input set and the dynamically changing image set to prune the search space of all solutions, (3) BDDs are used to compute all solutions below intermediate points in the SAT decision tree, (4) a negrained variable quanti cation schedule is used for each BDD subproblem, based on the CNF representation of the Boolean relation. These enhancements coupled with more engineering heuristics lead to an overall algorithm that can potentially handle larger problems. This is supported by our preliminary results on exact reachability analysis of ISCAS benchmark circuits. 1
A novel SAT allsolutions solver for efficient preimage computation
 Proc. of Design, Automation and Test in Europe Conf
, 2004
"... In this paper, we present a novel allsolutions preimage SAT solver, SOLALL, with the following features: (1) a new successdriven learning algorithm employing smaller cut sets; (2) a marked CNF database nontrivially combining success/conflictdriven learning; (3) quantifiedjumpback dynamically q ..."
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Cited by 22 (0 self)
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In this paper, we present a novel allsolutions preimage SAT solver, SOLALL, with the following features: (1) a new successdriven learning algorithm employing smaller cut sets; (2) a marked CNF database nontrivially combining success/conflictdriven learning; (3) quantifiedjumpback dynamically quantifying primary input variables from the preimage; (4) improved free BDD built on the fly, saving memory and avoiding inclusion of PI variables; finally, (5) a practical method of storing all solutions into a canonical OBDD format. Experimental results demonstrated the efficiency of the proposed approach for very large sequential circuits. 1.
Progress on the State Explosion Problem in Model Checking
, 2000
"... Model checking is an automatic verification technique for finite state concurrent systems. In this approach to verification, temporal logic specifications are checked by an exhaustive search of the state space of the concurrent system. Since the size of the state space grows exponentially with th ..."
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Cited by 18 (1 self)
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Model checking is an automatic verification technique for finite state concurrent systems. In this approach to verification, temporal logic specifications are checked by an exhaustive search of the state space of the concurrent system. Since the size of the state space grows exponentially with the number of processes, model checking techniques based on explicit state enumeration can only handle relatively small examples. This phenomenon is commonly called the "State Explosion Problem". Over the past ten years considerable progress has been made on this problem by (1) representing the state space symbolically using BDDs and by (2) using abstraction to reduce the size of the state space that must be searched. As a result model checking has been used successfully to find extremely subtle errors in hardware controllers and communication protocols. In spite of these successes, however, additional research is needed to handle large designs of industrial complexity. This aim of this paper is to give a succinct survey of symbolic model checking and to introduce the reader to recent advances in abstraction. 1
FineGrain Conjunction Scheduling for Symbolic Reachability Analysis
 IN INTERNATIONAL CONFERENCE ON TOOLS AND ALGORITHMS FOR CONSTRUCTION AND ANALYSIS OF SYSTEMS (TACAS’02
, 2002
"... In symbolic model checking, image computation is the process of computing the successors of a set of states. Containing the cost of image computation depends critically on controlling the number of variables that appear in the functions being manipulated; this in turn depends on the order in whic ..."
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Cited by 16 (2 self)
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In symbolic model checking, image computation is the process of computing the successors of a set of states. Containing the cost of image computation depends critically on controlling the number of variables that appear in the functions being manipulated; this in turn depends on the order in which the basic operations of image computationconjunctions and quantificationsare performed. In this paper we propose an approach to this ordering problemthe conjunction scheduling problemthat is especially suited to the case in which the transition relation is specified as the composition of many small relations. (This is the norm in hardware verification.) Our finegrain approach leads to the formulation of conjunction scheduling in terms of minimum maxcut linear arrangement, an NPcomplete problem for which efficient heuristics have been developed. The cut whose width is minimized is related to the number of variables active during image computation. We also propose a clustering technique that is geared toward the minimization of the maxcut, and pruning techniques for the transition relation that benefit especially from the finegrain approach.
CirCUs: A hybrid satisfiability solver
 In International Conference on Theory and Applications of Satisfiability Testing (SAT 2004
, 2004
"... Abstract. CirCUs is a satisfiability solver that works on a combination of an AndInverterGraph (AIG), Conjunctive Normal Form (CNF) clauses, and Binary Decision Diagrams (BDDs). We show how BDDs are used by CirCUs to help in the solution of SAT instances given in CNF. Specifically, the clauses are ..."
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Cited by 13 (3 self)
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Abstract. CirCUs is a satisfiability solver that works on a combination of an AndInverterGraph (AIG), Conjunctive Normal Form (CNF) clauses, and Binary Decision Diagrams (BDDs). We show how BDDs are used by CirCUs to help in the solution of SAT instances given in CNF. Specifically, the clauses are sorted by solving a hypergraph linear arrangement problem. Then they are clustered by an algorithm that strives to avoid explosion in the resulting BDD sizes. If clustering results in a single diagram, the SAT instance is solved directly. Otherwise, search for a satisfying assignment is conducted on the original clauses, enhanced with information extracted from the BDDs. We also describe a new decision variable selection heuristic that is based on recognizing that the variables involved in a conflict clause are often best treated as a related group. We present experimental results that demonstrate CirCUs’s efficiency especially for mediumsize SAT instances that are hard to solve by traditional solvers based on DPLL. 1
A Symbolic Approach to the AllPairs ShortestPaths Problem
 In WG 2004, LNCS 3353
, 2004
"... Abstract. Graphs can be represented symbolically by the Ordered Binary Decision Diagram (OBDD) of their characteristic function. To solve problems in such implicitly given graphs, specialized symbolic algorithms are needed which are restricted to the use of functional operations offered by the OBDD ..."
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Cited by 12 (5 self)
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Abstract. Graphs can be represented symbolically by the Ordered Binary Decision Diagram (OBDD) of their characteristic function. To solve problems in such implicitly given graphs, specialized symbolic algorithms are needed which are restricted to the use of functional operations offered by the OBDD data structure. In this paper, a symbolic algorithm for the allpairs shortestpaths (APSP) problem in loopless directed graphs with strictly positive integral edge weights is presented. It requires Θ ( log 2 (NB) ) OBDDoperations to obtain the lengths and edges of all shortest paths in graphs with N nodes and maximum edge weight B. It is proved that runtime and space usage are polylogarithmic w. r. t. N and B on graph sequences with characteristic boundedwidth functions. This convenient property is closed under certain graph composition operations. Moreover, an alternative symbolic approach for general integral edge weights is sketched which does not behave efficiently on general graph sequences with boundedwidth functions. Finally, two variants of theAPSPproblemarebrieflydiscussed. 1
Simplifying Circuits for Formal Verification Using Parametric Representation
 in Formal Methods in ComputerAided Design
, 2002
"... We describe a new method to simplify combinational circuits while preserving the set of all possible values (that is, the range) on the outputs. This method is performed iteratively and on the fly while building BDDs of the circuits. ..."
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Cited by 11 (0 self)
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We describe a new method to simplify combinational circuits while preserving the set of all possible values (that is, the range) on the outputs. This method is performed iteratively and on the fly while building BDDs of the circuits.
Using Combinatorial Optimization Methods for Quantification Scheduling
"... Model checking is the process of verifying whether a model o a coK452wG t system satisfies a specified tempomp property. Symbolic algoP90wG basedo n Binary Decisio Diagrams (BDDs) have significantly increased the sizeo the mo dels that can be verified. The mainprow42 in symbo licmo del checking is t ..."
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Cited by 9 (0 self)
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Model checking is the process of verifying whether a model o a coK452wG t system satisfies a specified tempomp property. Symbolic algoP90wG basedo n Binary Decisio Diagrams (BDDs) have significantly increased the sizeo the mo dels that can be verified. The mainprow42 in symbo licmo del checking is the image computVN7B problem, i.e., e#ciently co4j97Kw the successoK o r predecesso5 o f a seto f states. This paper is an indepth studyo the imagecoew5O7j5w pro4Kj4 We analyze and evaluate several newheuristics, metrics, and algo979wG fo thisprow0P0 The algoj25wG use co binato0wG oto0wG4Pj2 techniques such as hill climbing,simulat d annealing,andordering by recursive partWBBVN3F to oO0 better results than was previo4wG the case. Theo70wG42 analysis and systematic experimentatio are used to evaluate the algoPKwG47