Results 1  10
of
95
The Constructive Semantics of Pure Esterel
, 1996
"... Esterel [8, 10, 3, 4] is an imperative synchronous parallel programming lan guage dedicated to reactive systems [17]. Esterel is tailored for programming hardware or software synchronous controllers for which the controlhandling aspects are predominant. Esterel programs are inputdriven: they wait ..."
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Cited by 90 (2 self)
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Esterel [8, 10, 3, 4] is an imperative synchronous parallel programming lan guage dedicated to reactive systems [17]. Esterel is tailored for programming hardware or software synchronous controllers for which the controlhandling aspects are predominant. Esterel programs are inputdriven: they wait for inputs and compute corresponding outputs in a cyclebased way. An in putoutput computation is called a reaction...
Multiway Decision Graphs for Automated Hardware Verification
, 1996
"... Traditional ROBDDbased methods of automated verification suffer from the drawback that they require a binary representation of the circuit. To overcome this limitation we propose a broader class of decision graphs, called Multiway Decision Graphs (MDGs), of which ROBDDs are a special case. With MDG ..."
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Cited by 77 (14 self)
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Traditional ROBDDbased methods of automated verification suffer from the drawback that they require a binary representation of the circuit. To overcome this limitation we propose a broader class of decision graphs, called Multiway Decision Graphs (MDGs), of which ROBDDs are a special case. With MDGs, a data value is represented by a single variable of abstract type, rather than by 32 or 64 boolean variables, and a data operation is represented by an uninterpreted function symbol. MDGs are thus much more compact than ROBDDs, and this greatly increases the range of circuits that can be verified. We give algorithms for MDG manipulation, and for implicit state enumeration using MDGs. We have implemented an MDG package and provide experimental results.
Markovian Analysis of Large Finite State Machines
 IEEE Transactions on CAD
, 1996
"... Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 ..."
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Cited by 66 (7 self)
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Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 27 states). These algorithms, based on Algebraic Decision Diagrams (ADDs)  an extension of BDDs that allows arbitrary values to be associated with the terminal nodes of the diagrams  determine the steadystate probabilities by regarding finite state machines as homogeneous, discreteparameter Markov chains with finite state spaces, and by solving the corresponding ChapmanKolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of systems we have implemented two solution techniques: One is based on the GaussJacobi iteration, the other one is based on simple matrix multiplication. Then we...
Efficient BDD Algorithms for FSM Synthesis and Verification
 In IEEE/ACM Proceedings International Workshop on Logic Synthesis, Lake Tahoe (NV
, 1995
"... We describe a set of BDD based algorithms for efficient FSM synthesis and verification. We establish that the core computation in both synthesis and verification is forming the image and preimage of sets of states under the transition relation characterizing the design. To make these steps as effic ..."
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Cited by 60 (2 self)
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We describe a set of BDD based algorithms for efficient FSM synthesis and verification. We establish that the core computation in both synthesis and verification is forming the image and preimage of sets of states under the transition relation characterizing the design. To make these steps as efficient as possible, we address BDD variable ordering, use of partitioned transition relations, and use of clustering. We provide an integrated set of algorithms and give references and comparisons with previous work. We report experimental results on a series of seven industrial examples containing from 28 to 172 binary valued latches. 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis, the science of optimizing designs (for ...
A Hardware Implementation of Pure Esterel
 ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, INDIAN ACADEMY OF SCIENCES, SADHANA
, 1991
"... Esterel is a synchronous concurrent programming language dedicated to reactive systems (controllers, protocols, manmachine interfaces, etc.). Esterel has an efficient standard software implementation based on welldefined mathematical semantics. We present a new hardware implementation of the pure ..."
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Cited by 58 (3 self)
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Esterel is a synchronous concurrent programming language dedicated to reactive systems (controllers, protocols, manmachine interfaces, etc.). Esterel has an efficient standard software implementation based on welldefined mathematical semantics. We present a new hardware implementation of the pure synchronization subset of the language. Each program generates a specific circuit that responds to any input in one clock cycle. When the source program satisfies some statically checkable dynamic properties, the circuit is shown to be semantically equivalent to the source program. The hardware translation has been effectively implemented on the programmable active memory Perle0 developed by J. Vuillemin and his group at Digital Equipment.
Efficient filtering in publishsubscribe systems using binary decision diagrams
 IN PROCEEDINGS OF THE 23TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING
, 2001
"... Implicit invocation or publishsubscribe has become an important architectural style for largescale system design and evolution. The publishsubscribe style facilitates developing largescale systems by composing separately developed components because the style permits loose coupling between vario ..."
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Cited by 56 (2 self)
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Implicit invocation or publishsubscribe has become an important architectural style for largescale system design and evolution. The publishsubscribe style facilitates developing largescale systems by composing separately developed components because the style permits loose coupling between various components. One of the major bottlenecks in using publishsubscribe systems for very large scale systems is the efficiency of filtering incoming messages, i.e., matching of published events with event subscriptions. This is a very challenging problem because in a realistic publishsubscribe system the number of subscriptions can be large. In this paper we present an approach for matching published events with subscriptions which scales to a large number of subscriptions. Our approach uses Binary Decision Diagrams, a compact data structure for representing boolean functions which has been successfully used in verification techniques such as model checking. Experimental results clearly demonstrate the efficiency of our approach.
BDS: A BDDBased Logic Optimization System
 Proc. of DAC 2000
, 2000
"... This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network e ..."
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Cited by 53 (0 self)
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This paper describes a new BDDbased logic optimization system, BDS. It is based on a recently developed theory for BDDbased logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.
Automatic Generation of Functional Vectors Using The Extended Finite State Machine Model
 ACM Trans. on design Automation of Electronic Systems
, 1996
"... We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms th ..."
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Cited by 45 (1 self)
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We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the highlevel description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model that is used to generate functional vectors. The EFSM model is a generalization of the traditional state machine model. It is a compact representation of models with local data variables and preserves many nice properties of a traditional state machine model. The theoretical background of the EFSM model will be addressed in this paper. Our method guarantees that the generated vectors cover every statement in the highlevel description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flipflops can be ge...
BDD variable ordering for interacting finite state machines
 IN PROC. OF THE DESIGN AUTOMATION CONF
, 1994
"... We address the problem of obtaining good variable orderings for the BDD representation of a system of interacting finite state machines (FSMs). Orderings are derived from the communication structure of the system. Communication complexity arguments are used to prove upper bounds on the size of the B ..."
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Cited by 41 (7 self)
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We address the problem of obtaining good variable orderings for the BDD representation of a system of interacting finite state machines (FSMs). Orderings are derived from the communication structure of the system. Communication complexity arguments are used to prove upper bounds on the size of the BDD for the transition relation of the product machine in terms of the communication graph, and optimal orderings are exhibited for a variety of regular systems. Based on the bounds we formulate algorithms for variable ordering. We perform reached state analysis on a number of standard verification benchmarks to test the effectiveness of our ordering strategy; experimental results demonstrate the e cacy of our approach. The algorithms described in this paper have been implemented in HSIS, a hierarchical synthesis and verification tool currently under development at Berkeley.
Approximation and Decomposition of Binary Decision Diagrams
, 1998
"... Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. ..."
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Cited by 29 (0 self)
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Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. In this paper we present a new algorithm for approximation and analyze its performance in comparison with existing techniques. We also introduce a new decomposition algorithm that produces balanced partitions. The effectiveness of our contributions is demonstrated by improved results in reachability analysis for some hard problem instances. 1 Introduction Symbolic state enumeration techniques based on Binary Decision Diagrams (BDDs [2]) have revolutionized formal verification [8, 4, 17, 1, 14]. They have two key features that make them suitable to the exploration of very large state graphs: They represent sets compactly, and they avoid explicit enumeration in image computation. Given the t...