We are building a very high performance 1.2 Gb/s ATM network interface chip called the APIC (ATM Port Interconnect Controller). In addition to borrowing useful ideas from a number of research and commercial prototypes, the APIC design embraces several innovative features, and integrates all of these pieces into a coherent whole. This paper describes some of the novel ideas that have been incorporated in the APIC design with a view to improving the bandwidth and latency seen by end-applications. Among the techniques described, Protected DMA and Protected I/O were designed to allow applications to queue data for transmission or reception directly from user-space, effectively bypassing the kernel. This argues for moving the entire protocol stack including the interface device driver into user-space, thereby yielding better latency and throughput performance than kernel-resident implementations. Pool DMA when used with Packet Splitting, is a technique that can be used to build true zero-co...

A significant driver for the consumer use of high bandwidth in the near future will be interactive video on demand (IVOD). A range of service types can be deployed, based on a differing sophistication, which must be traded against the network costs (bandwidth) and component costs (switch complexity and memory). The potential aggregate bandwidth required is huge (O(1Pbps)), and thus it is essential to properly engineer the network to reduce the bandwidth required. This paper describes a variety of IVOD scenarios, and introduces a cost function that captures the combined bandwidth and storage requirements of the network. This cost function is used to compare different network engineering alternatives, particularly program caching and stream sharing. The effects of nonlinear pricing and differing weights of bandwidth and storage are also reflected by the cost function. This cost function can be used by network designers to determine optimal topology, sharing, and caching strategies for ...

. We describe a framework for providing quality-of-service guarantees within the endsystem for networked multimedia applications. Our framework integrates four components namely, QoS specification, QoS mapping, QoS enforcement, and a protocol implementation model. The framework allows QoS specifications to be at a high level so that an application can easily specify its requirements using a small number of parameters. The second component of the framework is QoS mapping. The mapping operations derive resource requirements for each end-toend session from the QoS parameters specified by the application. Important resources considered are the cpu and the network connection. The third component of the framework is QoS enforcement. An important enforcement issue is providing processing guarantees for protocol code. An efficient real-time signal facility (RTSig) has been implemented to achieve this. The last component is an application level protocol implementation model. Protocol code struc...

The last few years have seen network data rates skyrocket from a few Mbps to a Gbps or more. However, a lack of integration of the host-network interface, the operating system, and network protocols has resulted in end-applications seeing only a small fraction of this total bandwidth being available for data transfer. The emergence of demanding applications in the realms of multimedia and virtual reality provides further impetus in the drive to overcome this problem. In this paper, we present the design of a high performance ATM host-network interface for workstations and servers that can support a bidirectional sustained data rate in excess of a gigabit per second. A prototype of the interface is being built at Washington University as part of an ARPA-sponsored gigabit local ATM testbed. Our interface design, which emphasizes seamless integration with the OS and network protocols, features: support for streaming data from I/O devices (e.g., cameras, disk arrays, etc.) to the network o...

The problem this paper addresses is how to modify an existing operating system’s I/O subsystem to support new high-speed networks and high-bandwidth multimedia applications that will play an important role in future computing environments. The proposed I/O subsystem is called universal continuous media I/O (UCM I/O). This paper will cover the preliminary design of UCM I/O, some of the trade-offs and issues that need to be addressed in order to implement UCM I/O, and a a summary

. Existing and upcoming distributed multimedia applications require highly diverse services to satisfy their communication needs. Service integrated communication systems should be capable of providing high-performance real-time multipoint communication service with guaranteed quality of service (QoS). Existing communication systems and known strategies for resource reservation face increasing difficulties in fulfilling these requirements, in particular in high-speed wide area networks. Therefore, new concepts are required to support the variety of emerging applications in a heterogeneous internetworking environment. In this paper, a framework for real-time multipeer services is presented. It is based on the separation of service requirements into network bearer and transfer service requirements. The transfer service enhances the network bearer service in order to meet the service requirements of the applications. Applications and transport systems interact using an enhanced service in...

Implementation platforms for integrated service communication subsystems providing high performance capabilities are increasingly required. In order to provide high performance, dedicated VLSI components can be used for time-critical processing tasks such as retransmission support or memory management. A modular VLSI implementation architecture designed with specialized components allows for service flexibility. The components can be parametrized and may be selected individually dependent on the service required by the application. The implementation architecture is not limited to a certain protocol and allows the implementation of high-speed protocols with fixed size packet headers. The paper describes the architecture in general and dedicated parts in more detail. Preliminary performance values are presented and compared with measurements of typical software implementations. 1 Introduction Emerging applications, mostly, require both high performance as well as support of a wide var...

We describe a framework for providing quality-of-service (QoS) guarantees within the endsystem for networked multimedia applications. There are four components in this framework namely---QoS specification, QoS mapping, QoS enforcement, and protocol implementation. QoS specifications are at a high level, and use a small number of parameters to allow applications greater ease in specifying their requirements. Based on the QoS specifications, QoS mapping operations derive resource requirements for each end-to-end session of the application. Important resources considered are the cpu and the network connection. The third component of the framework is QoS enforcement. Enforcement is mainly concerned with providing real-time processing guarantees for protocol code during data transfer. We have implemented a real-time upcall (rtu) facility which is an enhancement to the well known upcall mechanism for structuring protocols. rtus are scheduled using a policy called rate monotonic with delayed...

One of the ways in which the APIC addresses the memory bottleneck alluded to above is to function in a desk-area environment where different memories can be used to spread the load. The idea here is to dedicate one APIC chip and one memory bank to each high-bandwidth device in the system, thereby shedding the load from a host system's main memory. Several such APIC-memory device combinations can be daisy chained to form a desk-area network with high bandwidth and low latency characteristics.

Service requirements and performance needs are increasingly demanding in emerging high performance communication subsystems. Wellsuited protocols and efficient protocol implementation techniques form the core of such systems. Applying parallelism and introducing VLSIcomponents to overcome system bottlenecks represent promising approaches towards highly efficient implementations. This paper discusses experiments with parallel protocol implementations and introduces a protocol especially designed to support parallelism. Moreover, a parallel VLSI architecture is introduced enabling fine-grained parallelism among protocol functions as well as coarse-grain parallelism among connections. Dedicated VLSI components are used for potential bottleneck functions, such as timer and memory management or retranmission support. 1 Introduction During the last few years the communication world has seen remarkable changes. Applications are becoming increasingly complex and require higher performance. A...