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Fault Identification via Nonparametric Belief Propagation
 SUBMITTED TO IEEE TRANS. ON SIGNAL PROCESSING
"... We consider the problem of identifying a pattern of faults from a set of noisy linear measurements. Unfortunately, maximum a posteriori probability estimation of the fault pattern is computationally intractable. To solve the fault identification problem, we propose a nonparametric belief propagatio ..."
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We consider the problem of identifying a pattern of faults from a set of noisy linear measurements. Unfortunately, maximum a posteriori probability estimation of the fault pattern is computationally intractable. To solve the fault identification problem, we propose a nonparametric belief propagation approach. We show empirically that our belief propagation solver is more accurate than recent stateoftheart algorithms including interior point methods and semidefinite programming. Our superior performance is explained by the fact that we take into account both the binary nature of the individual faults and the sparsity of the fault pattern arising from their rarity.
Multiple fault diagnosis of analog circuits by locating ambiguity groups of test equation
 Proc. of Int. Symp. Circuits and Systems
, 2001
"... This paper proposes a method to diagnose the multiple faults in the linear analog circuits. Test equation establishes the relationship between the measured responses and faulty excitations due to faulty elements. The QR factorization is applied to identify ambiguity groups in the test verification m ..."
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This paper proposes a method to diagnose the multiple faults in the linear analog circuits. Test equation establishes the relationship between the measured responses and faulty excitations due to faulty elements. The QR factorization is applied to identify ambiguity groups in the test verification matrix. The suspicious faulty excitations of the minimum size are determined. Faulty parameters are evaluated using the structural incident signal matrix. Finally this method is illustrated with an example circuit. 1.
Impulse Response fault model and Fault Extraction for Functional Level Analog Circuit Diagnosis
 In: IEEE International Conference on CAD, proceedings...1995
, 1995
"... In this paper, a functional fault model for analog circuit diagnosis is proposed. A faulty circuit is modeled as a faultfree module in serial or in parallel with a fault module. To extract the faults, we adopt an iterative deconvolution technique to deconvolute the impulse response of the fault mod ..."
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In this paper, a functional fault model for analog circuit diagnosis is proposed. A faulty circuit is modeled as a faultfree module in serial or in parallel with a fault module. To extract the faults, we adopt an iterative deconvolution technique to deconvolute the impulse response of the fault module from the faulty response. Such impulse response fault modeling makes the faults independent of input signals and system function. As the test results show, the input independent property significantly improves the diagnostic resolution, and the system function independent property allows singlemodule fault tables to be applied to multimodule diagnosis.
Development of decomposition approach for testing large analog circuits
, 1989
"... Abstract. This article presents an efficient method for testing large scale analog and mixed mode networks. Test equations are derived lbr a partitioned network from Krichhoff current law equations at the partition points. Voltages at the partition points are used to identify network pararneters. Th ..."
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Abstract. This article presents an efficient method for testing large scale analog and mixed mode networks. Test equations are derived lbr a partitioned network from Krichhoff current law equations at the partition points. Voltages at the partition points are used to identify network pararneters. Thc method has applications to circuit modeling, fault diagnosis, testing and calibration. The conventional testing methods for dynamic, nonlinear networks are based on the sensitivity approach, which uses incremental changes in voltages to estimate changes in network parameters. However, this conventional approach cannot handle large scale circuits because the sensitivity matrix is dense. This results in enormous requirements for memory space and computing time when the circuit size becomes large. The new method overcomes these deficiencies of the sensitivity approach. In this article, we introduce the decomposition method, describe its basic features and its algorithm. and compare this method with a conventional. sensitivity technique using testing network examples.
Automatic Test Generation for Maximal Diagnosis of Linear Analog Circuits
 Proc. European Design & Test Conf
, 1996
"... A faultbased multifrequency test generation and fault diagnosis procedureisproposed in this work. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis of circuit AC hard#soft faults. The pr ..."
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A faultbased multifrequency test generation and fault diagnosis procedureisproposed in this work. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis of circuit AC hard#soft faults. The procedure is exempli #ed for several selftestable linear analog circuits. 1 Introduction The rapid growth in the deploymentofhybrid analog #digital circuits has strengthened the need of addressing test and diagnosis issues for analog circuits. In the digital case, test and diagnosis techniques have been successfully developed and automated. This is not yet the case for analog circuits. Analog fault diagnosis has been addressed bytwo general methods: simulatebeforetest #SBT# and simulateaftertest #SAT# #1#. The former is based on the use of fault dictionaries. The latter uses measurements to compute parameters of the network or locate the faulty components. SAT approaches rely on solvi...
Partial simulationdriven ATPG for detection and diagnosis of faults in analog circuits
 in Proc. IEEE/ACM Int. Conf. ComputerAided Design
"... In this paper, we propose a novel faultoriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuitundertest, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set ..."
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In this paper, we propose a novel faultoriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuitundertest, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set of faults. It also computes the optimal set of test nodes to probe at, and the time instants to make measurements. The test generation program accommodates the effects introduced by component tolerances and measurement inaccuracy, and can be tailored to fit the signal generation capabilities of a hardware tester. Experimental results show that the proposed technique can be applied to generate transient tests for both linear and nonlinear analog circuits of moderate complexity in reasonably less CPU time. This will significantly impact the test development costs for an analog circuit and will decrease the timetomarket of a product. Finally, the short duration and the easytoapply feature of the test stimuli will lead to significant reduction in production test costs. 1.
Soft Fault Diagnosis in Analog Circuit Based on Fuzzy and Direction
, 2009
"... A basic circuit theory of fault diagnosis for analog circuits with parameter tolerance is proposed in this paper. The approach uses the direction vector of voltage increment in test nodes as a fault signature for predefined faults. A linear equation is built to locate a faulty element. On the condit ..."
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A basic circuit theory of fault diagnosis for analog circuits with parameter tolerance is proposed in this paper. The approach uses the direction vector of voltage increment in test nodes as a fault signature for predefined faults. A linear equation is built to locate a faulty element. On the condition that the component tolerances are taken into account, the concepts of direction vector and fuzzy analysis method are combined together to analyze a parametric fault. Examples illustrate the proposed approach and show its effectiveness.
Probabilistic Graphical Models for the Diagnosis of Analog Electrical Circuits
"... Abstract. We describe an algorithm to build a graphical model—more precisely: a join tree representation of a Markov network—for a steady state analog electrical circuit. This model can be used to do probabilistic diagnosis based on manufacturer supplied information about nominal values of electrica ..."
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Abstract. We describe an algorithm to build a graphical model—more precisely: a join tree representation of a Markov network—for a steady state analog electrical circuit. This model can be used to do probabilistic diagnosis based on manufacturer supplied information about nominal values of electrical components and their tolerances as well as measurements made on the circuit. Faulty components can be identified by looking for high probabilities for values of characteristic magnitudes that deviate from the nominal values. 1
On Ycompatible and strict Ycompatible functions
, 1997
"... Let Y 2 IR n . A function f : IR n ! IR k Y compatible, if for any Z 2 IR n , Z Y if and only if f(Z) f(Y ) and is strict Y compatible, if for any Z 2 IR n , Z ! Y if and only if f(Z) ! f(Y ). It is proved that for any Y 2 IR n , n 2, there is no Y compatible polynomial function f ..."
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Let Y 2 IR n . A function f : IR n ! IR k Y compatible, if for any Z 2 IR n , Z Y if and only if f(Z) f(Y ) and is strict Y compatible, if for any Z 2 IR n , Z ! Y if and only if f(Z) ! f(Y ). It is proved that for any Y 2 IR n , n 2, there is no Y compatible polynomial function f : IR n ! IR k , 1 k ! n. It is also proved that for a strict Y compatible map f , J f (Y ) = 0, where J f (Y ) denote the Jacobian matrix of the mapping f in Y . These problems arose in studying data compression of analog signatures. 1 Introduction This work was initiated by the problems of storage and processing of measured response data of analog circuits normally used by the fault dictionary techniques in fault localization [1], [2]. We explore the possibility of data compression of a series of real numbers representing given response data. In particular, we are looking for some data compression function that would enable us to determine for any two given responses y 1 , y 2 , : ...
A DECOMPOSITION METHOD FOR ANALOG FAULT LOCATION
"... In this paper, fault location in large analog networks by decomposition method is generalized to include subnetworks not explicitly testable. Assume that the network topology and nominal values of network components are known and the networkundertest is partitioned into subnetworks once for all. Th ..."
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In this paper, fault location in large analog networks by decomposition method is generalized to include subnetworks not explicitly testable. Assume that the network topology and nominal values of network components are known and the networkundertest is partitioned into subnetworks once for all. The decomposition nodes could be either the accessible nodes whose nodal voltages can be measured or the inaccessible nodes whose nodal voltages under faulty condition can be computed by a new method proposed in this paper. The new method reduces the test requirements for the number of accessible nodes and increases the flexibility of decomposition. Location of faulty subnetworks and subsequent location of faulty components are implemented based on checking consistency of the KCL equations for the decomposition nodes and using ambiguity group location techniques. This method can be applied to linear or nonlinear networks, and is particularly effective for the large scale analog networks. An example circuit is provided to illustrate the efficiency of the proposed method. 1.