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201
A static power model for architects
 In Proceedings of the 33rd International Symposium on Microarchitecture (MICRO33
, 2000
"... Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations ..."
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Cited by 131 (2 self)
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Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level: Pstatic = VCC ⋅ N ⋅ kdesign ⋅ Îleak, where VCC is the supply voltage, N is the number of transistors, kdesign is a design dependent parameter, and Îleak is a technology dependent parameter. This model enables highlevel reasoning about the likely static power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the highlevel designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty. 1.
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads
, 2002
"... Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS ca ..."
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Cited by 105 (2 self)
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Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in highperformance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct tradeoff between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness· of our approach is evaluated on real workloads obtained using realtime monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.
Supply and threshold voltage scaling for low power CMOS
 IEEE Journal of solidState Circuits
, 1997
"... Abstract — This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a firstorder model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially whe ..."
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Cited by 97 (4 self)
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Abstract — This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a firstorder model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor. In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields. Index Terms — Energydelay product, low power CMOS circuits, threshold scaling. I.
Figures of Merit to Characterize the Importance of OnChip Inductance
 Proceedings of the IEEE/ACM Design Automation Conference
, 1998
"... A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be ..."
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Cited by 75 (24 self)
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A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC P circuit based on a 0.25 m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it ...
DualThreshold Voltage Techniques for LowPower Digital Circuits
 IEEE Journal of SolidState Circuits
, 2000
"... Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dualthreshold voltage techniques for reducing standby power dissipation while still maintaining high p ..."
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Cited by 69 (3 self)
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Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dualthreshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual domino logic style that provides the performance equivalent of a purely low design with the standby leakage characteristic of a purely high implementation is also proposed.
A Dynamic Voltage Scaling Algorithm for DynamicPriority Hard RealTime Systems Using Slack Time Analysis
 In Proceedings of Design Automation and Test in Europe
, 2002
"... Dynamic voltage scaling (DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded realtime systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in i ..."
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Cited by 68 (11 self)
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Dynamic voltage scaling (DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded realtime systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. In this paper, we propose a novel DVS algorithm for periodic hard realtime tasks based on an improved slack estimation algorithm. Unlike the existing techniques, the proposed method takes full advantage of the periodic characteristics of the realtime tasks under prioritydriven scheduling such as EDF. Experimental results show that the proposed algorithm reduces the energy consumption by 20#40% over the existing DVS algorithm. The experiment results also show that our algorithm based on the improved slack estimation method gives comparable energy savings to the DVS algorithm based on the theoretically optimal (but impractical) slack estimation method.
Repeater Design to Reduce Delay and Power in Resistive Interconnect
 IEEE Trans. Circuits Syst. II
, 1998
"... Abstract—In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing shortcircu ..."
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Cited by 49 (19 self)
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Abstract—In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing shortcircuit current. In order to develop a repeater design methodology, a timing model characterizing a complementary metal–oxide–semiconductor (CMOS) inverter driving a resistance–capacitance (‚g ‚g) ‚g load is presented. The model is based on the Sakurai shortchannelpower law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical ‚g loads, this analytical repeater model exhibits a maximum error of 16 % as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus taperedbuffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and taperedbuffer repeaters even with relatively small resistive ‚g loads. An expression for the shortcircuit power dissipation of a repeater driving an ‚g load is presented. A comparison of the shortcircuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made. Index Terms — Buffer insertion, delay optimization, RC interconnect, repeaters.
VariationAware Application Scheduling and Power Management for Chip Multiprocessors
, 2008
"... Withindie process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Freq ..."
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Cited by 47 (5 self)
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Withindie process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variationaware algorithms for application scheduling and power management. One such power management algorithm, called LinOpt, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP — maximizing throughput at a given power budget. In a 20core CMP, the combination of variationaware application scheduling and LinOpt increases the average throughput by 12–17 % and reduces the average ED 2 by 30–38 % — all relative to using variationaware scheduling together with a simple extension to Intel’s Foxton power management algorithm.
Practical VoltageScaling for FixedPriority RTSystems
 In Proceedings of the 9 th IEEE RealTime and Embedded Technology and Applications Symposium (RTAS’03
, 2003
"... 1 Introduction The field of dynamic voltage scaling is currently the focus of a great deal of research interest with the goal of achieving energy efficiency in portable systems and servers. This is due to the fact that the dynamic power consumption of CMOS circuits [16, 19] is given by P = aC L ..."
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Cited by 45 (0 self)
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1 Introduction The field of dynamic voltage scaling is currently the focus of a great deal of research interest with the goal of achieving energy efficiency in portable systems and servers. This is due to the fact that the dynamic power consumption of CMOS circuits [16, 19] is given by P = aC L