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Information Theory and Communication Networks: An Unconsummated Union
 IEEE Trans. Inform. Theory
, 1998
"... Information theory has not yet had a direct impact on networking, although there are similarities in concepts and methodologies that have consistently attracted the attention of researchers from both fields. In this paper, we review several topics that are related to communication networks and that ..."
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Cited by 133 (5 self)
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Information theory has not yet had a direct impact on networking, although there are similarities in concepts and methodologies that have consistently attracted the attention of researchers from both fields. In this paper, we review several topics that are related to communication networks and that have an information theoretic flavor, including multiaccess protocols, timing channels, effective bandwidth of bursty data sources, deterministic constraints on datastreams, queueing theory, and switching networks. Keywords Communication networks, multiaccess, effective bandwidth, switching I. INTRODUCTION Information theory is the conscience of the theory of communication; it has defined the "playing field" within which communication systems can be studied and understood. It has provided the spawning grounds for the fields of coding, compression, encryption, detection, and modulation and it has enabled the design and evaluation of systems whose performance is pushing the limits of wha...
MULTIPROCESSOR SCHEDULING TO ACCOUNT FOR INTERPROCESSOR COMMUNICATION
, 1991
"... Interprocessor communication (PC) overheads have emerged as the major performance limitation in parallel processing systems, due to the transmission delays, synchronization overheads, and conflicts for shared communication resources created by data exchange. Accounting for these overheads is essenti ..."
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Cited by 67 (11 self)
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Interprocessor communication (PC) overheads have emerged as the major performance limitation in parallel processing systems, due to the transmission delays, synchronization overheads, and conflicts for shared communication resources created by data exchange. Accounting for these overheads is essential for attaining efficient hardware utilization. This thesis introduces two new compiletime heuristics for scheduling precedence graphs onto multiprocessor architectures, which account for interprocessor communication overheads and interconnection constraints in the architecture. These algorithms perform scheduling and routing simultaneously to account for irregular interprocessor interconnections, and schedule all communications as well as all computations to eliminate shared resource contention. The first technique, called dynamiclevel scheduling, modifies the classical HLFET list scheduling strategy to account for IPC and synchronization overheads. By using dynamically changing priorities to match nodes and processors at each step, this technique attains an equitable tradeoff between load balancing and interprocessor communication cost. This method is fast, flexible, widely targetable, and displays promising perforrnance. The second technique, called declustering, establishes a parallelism hierarchy upon the precedence graph using graphanalysis techniques which explicitly address the tradeoff between exploiting parallelism and incurring communication cost. By systematically decomposing this hierarchy, the declustering process exposes parallelism instances in order of importance, assuring efficient use of the available processing resources. In contrast with traditional clustering schemes, this technique can adjust the level of cluster granularity to suit the characteristics of the specified architecture, leading to a more effective solution.
Packet Routing In FixedConnection Networks: A Survey
, 1998
"... We survey routing problems on fixedconnection networks. We consider many aspects of the routing problem and provide known theoretical results for various communication models. We focus on (partial) permutation, krelation routing, routing to random destinations, dynamic routing, isotonic routing ..."
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Cited by 29 (3 self)
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We survey routing problems on fixedconnection networks. We consider many aspects of the routing problem and provide known theoretical results for various communication models. We focus on (partial) permutation, krelation routing, routing to random destinations, dynamic routing, isotonic routing, fault tolerant routing, and related sorting results. We also provide a list of unsolved problems and numerous references.
A Fast Packet Switch for the Integrated Services Backbone Network
, 1988
"... With the projected growth in demand for bandwidth and telecommunications services will come the requirement for a multiservice backbone network of far greater efficiency, capacity, and flexibility than the ISDN is able to satisfy. This class of network has been termed the broadband ISDN, and the des ..."
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Cited by 9 (2 self)
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With the projected growth in demand for bandwidth and telecommunications services will come the requirement for a multiservice backbone network of far greater efficiency, capacity, and flexibility than the ISDN is able to satisfy. This class of network has been termed the broadband ISDN, and the design of the switching nodes of such a network is the subject of much current research. This paper investigates one possible solution. The design and performance, for multiservice traffic, is presented of a fast packet switch based upon a nonbuffered, multistage interconnection network. It is shown that for an implementation in current CMOS technology, operating at 50 MHz, switches with a total traffic capacity of up to 150 Gbit/s may be constructed. Furthermore, if the reserved service traffic load is limited on each input port to a maximum of 80 percent of switch port saturation, then a maximum delay across the switch of the order of 100 s may be guaranteed, for 99 percent of the reserved se...
SXmin: A SelfRouting HighPerformance ATM Packet Switch Based on GroupKnockout Principle
, 1997
"... We propose SXmin: a self routing, group Knockout Principle [15] based ATM packet switch which provides comparable delaythroughput performance and packet loss probabilities at significantly reduced hardware requirements compared to earlier switches [6,12,13,15,17]. The N \Theta N SXmin consists of a ..."
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Cited by 7 (1 self)
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We propose SXmin: a self routing, group Knockout Principle [15] based ATM packet switch which provides comparable delaythroughput performance and packet loss probabilities at significantly reduced hardware requirements compared to earlier switches [6,12,13,15,17]. The N \Theta N SXmin consists of an N \Theta N Batcher sorter followed by log 2 N \Gamma 1 stages of sortexpander (SX) modules arranged in the form of a complete binary tree. Each SX module consists of a column of 2 \Theta 2 switches with a wraparoundunshuffle inputoutput interconnection. This enables the hierarchical utilization of the group Knockout Principle to expand the number of inputs by a small factor at each stage, resulting in a significant reduction in overall hardware complexity. Routing at each switch is controlled by a single bit. However, in case of contention, a dual bit resolution algorithm is used locally which drops excess packets in a predetermined manner while ensuring global randomness of packet loss over the entire switching network. There are no internal buffers at the individual stages and therefore the internal delay is constant and proportional to the number of stages. The use of simple hardware components and regular interconnections in the SX modules makes the network suitable for optical implementation.
Spatial Division Multiplexing: a Novel Approach for Guaranteed Throughput on NoCs
 In: International Conference on Hardware Software Codesign
, 2005
"... To ensure low power consumption while maintaining flexibility and performance, future SystemsonChip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, NetworksonChip (NoC) have been propos ..."
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Cited by 7 (0 self)
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To ensure low power consumption while maintaining flexibility and performance, future SystemsonChip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, NetworksonChip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. Stateoftheart NoCs currently exploit TimeDivision Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit setup time. We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDMbased network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.
Efficient VLSI Implementation of Iterative Solutions to Sparse Linear Systems
, 1989
"... We propose a novel way of solving systems of linear equations with sparse coefficient matrices using iterative methods on a VLSI array. The nonzero entries of the coefficient matrix are mapped onto a processor array of size p e \Theta p e, where e is the number of nonzero elements, n is the numbe ..."
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Cited by 4 (1 self)
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We propose a novel way of solving systems of linear equations with sparse coefficient matrices using iterative methods on a VLSI array. The nonzero entries of the coefficient matrix are mapped onto a processor array of size p e \Theta p e, where e is the number of nonzero elements, n is the number of equations and e n. The data transport problem that arises because of this mapping is solved using an efficient routing technique. Preprocessing is carried out on the iteration matrix of the system to compute the routing controlwords that are used in the data transfer. This results in O( p e) time for each iteration of the method, with a small constant factor. As compared to existing VLSI methods for solving the problem, the proposed method yields a superior time performance, greater ease of programmability and an area efficient design. We also develop a second implementation of our algorithm that uses a slightly higher number of communication steps, but reduces the number of arithme...
Fast Packet Switching for Integrated Services
 University of Cambridge Computer Laboratory
, 1988
"... As the communications industry continues to expand two current trends are becoming apparent: the desire to support an increasing diversity of communications services #voice, video, image, text, etc.# and the consequent requirement for increased network capacity to handle the expected growth in suchm ..."
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Cited by 4 (1 self)
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As the communications industry continues to expand two current trends are becoming apparent: the desire to support an increasing diversity of communications services #voice, video, image, text, etc.# and the consequent requirement for increased network capacity to handle the expected growth in suchmultiservice tra#c. This dissertation describes the design, performance and implementation of a high capacity switch which uses fast packet switching to o#er the integrated support of multiservice tra#c. Applications for this switch are considered within the public network, in the emerging metropolitan area network and within local area networks. The Cambridge Fast Packet Switch is based upon a nonbu#ered, multipath switch fabric with packet bu#ers situated at the input ports of the switch. This results in a very simple implementation suitable for construction in current gate array technology. A simulation study of the throughput at saturation of the switch is #rst presented to select th...
Widesense nonblocking Clos networks under packing strategy
 IEEE Trans. Computers
, 1999
"... AbstractÐIn this paper, we study widesense nonblocking conditions under packing strategy for the threestage Clos network, or v…m; n; r † network. Widesense nonblocking networks are generally believed to have lower network cost than strictly nonblocking networks. However, the analysis for the wide ..."
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Cited by 4 (1 self)
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AbstractÐIn this paper, we study widesense nonblocking conditions under packing strategy for the threestage Clos network, or v…m; n; r † network. Widesense nonblocking networks are generally believed to have lower network cost than strictly nonblocking networks. However, the analysis for the widesense nonblocking conditions is usually more difficult. Moore (cited injk Benes ' book [2]) proved that a v…m; n; 2 † network is nonblocking under packing strategy ifthe number ofmiddle stage switches m. This result has been widely cited in the literature, and is even considered as the widesense nonblocking condition under packing strategy for the 3 general v…m; n; r † networks in some papers, such as [7]. In fact, it is still not known that whether the condition m 2 n jk holds for v…m; n; r † networks when r 3. In this paper, we introduce a systematic approach to the analysis ofwidesense nonblocking conditions for general v…m; n; r † networks with any r value. We first translate the problem of finding the nonblocking condition under packing strategy for a v…m; n; r † network to a set oflinear programming problems. We then solve this special type oflinear programming problems and obtain a closed form optimum solution. We prove that the necessary condition for a v…m; n; r † network to be nonblocking 1 under packing strategy is m 2 F2r 1 n j k, where F2r 1 is the Fibonacci number. In the case of n F2r 1, this condition is also a sufficient nonblocking condition for packing strategy. We believe that the systematic approach developed in this paper can be used for analyzing other widesense nonblocking control strategies as well. Index TermsÐInterconnection networks, widesense nonblocking, routing control strategies, packing, linear programming, Fibonacci numbers. 1
Puzzling Permutations
 In Proc. Glasgow Functional Programming Workshop
, 1996
"... We showhow to describe and analyse multistage interconnection networks in a relational framework. We give simple elegant descriptions of butterfly networks, using only two functions for building networks from smaller networks. By studying the algebra of these functions, we can give a clear account o ..."
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Cited by 2 (1 self)
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We showhow to describe and analyse multistage interconnection networks in a relational framework. We give simple elegant descriptions of butterfly networks, using only two functions for building networks from smaller networks. By studying the algebra of these functions, we can give a clear account of the properties of networks, without resorting to the standard methods of reasoning in terms of binary representations of the addresses of data elements. The paper is intended as a tutorial introduction to multistage interconnection networks. 1