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17
Probabilistic synaptic weighting in a reconfigurable network of VLSI integrateandfire neurons
 NEURAL NETWORKS
, 2001
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Multichannel coherent detection for delayinsensitive modelfree adaptive control
 in Proc. Int. Symp. Circuits and Systems (ISCAS ’07
, 2007
"... Abstract — A mixedsignal architecture for continuoustime multidimensional modelfree optimization is presented. It is based on multichannel coherent modulation and detection that reliably estimates the objective function’s gradient, with respect to the system parameters, in the presence of time d ..."
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Cited by 5 (5 self)
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Abstract — A mixedsignal architecture for continuoustime multidimensional modelfree optimization is presented. It is based on multichannel coherent modulation and detection that reliably estimates the objective function’s gradient, with respect to the system parameters, in the presence of time delays. The narrowband nature of the excitation signals reduces the unknown dynamics of the objective function to a single parameter per control channel, the phase delay. An efficient implementation of the adaptive control architecture is presented; it incorporates parallel control channels with individually selectable 6level phase delay adjustment. Initial experimental results indicate wide operating range covering almost 7 decades of excitation frequencies. I.
Image sharpness and beam focus vlsi sensors for adaptive optics
 IEEE Sensors Journal
, 2002
"... Abstract—Highresolution wavefront control for adaptive optics requires accurate sensing of a measure of optical quality. We present two analog verylargescaleintegration (VLSI) imageplane sensors that supply realtime metrics of image and beam quality, for applications in imaging and lineofsig ..."
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Cited by 4 (1 self)
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Abstract—Highresolution wavefront control for adaptive optics requires accurate sensing of a measure of optical quality. We present two analog verylargescaleintegration (VLSI) imageplane sensors that supply realtime metrics of image and beam quality, for applications in imaging and lineofsight laser communication. The image metric VLSI sensor quantifies sharpness of the received image in terms of average rectified spatial gradients. The beam metric VLSI sensor returns first and second order spatial moments of the received laser beam to quantify centroid and width. Closedloop wavefront control of a laser beam through turbulence is demonstrated using a spatial phase modulator and analog VLSI controller that performs stochastic parallel gradient descent of the beam width metric. Index Terms—Adaptive optics, analog very large scale integration (VLSI), focalplane image processing, image sensors, optical communication. I.
HighSpeed, ModelFree Adaptive Control Using Parallel Synchronous Detection ABSTRACT
"... A VLSI implementation of an adaptive controller performing gradient descent optimization of external performance metrics using parallel synchronous detection is presented. Realtime modelfree gradient estimation is done by perturbation of the metrics ’ control parameters with narrowband determinis ..."
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Cited by 3 (3 self)
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A VLSI implementation of an adaptive controller performing gradient descent optimization of external performance metrics using parallel synchronous detection is presented. Realtime modelfree gradient estimation is done by perturbation of the metrics ’ control parameters with narrowband deterministic dithers resulting in fast adaptation and robust performance. A fully translinear design has been employed for the architecture, making the controller operation scalable within a very wide range of frequencies and control bandwidths, and, therefore customizable for a variety of systems and applications. Experimental results from a SiGe BiCMOS implementation are provided demonstrating the broadband and highspeed performance of the controller.
VLSI neural network with digital weights and analog multipliers
 Proceedings of the 2001 IEEE International Symposium on Circuits and Systems ISCAS 2001
, 2001
"... A VLSI feedforward neural network is presented that makes use of digital weights and analog multipliers. The network is trained in a chipinloop fashion with a host computer implementing the training algorithm. The chip uses a serial digital weight bus implemented by a long shift register to input ..."
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Cited by 3 (1 self)
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A VLSI feedforward neural network is presented that makes use of digital weights and analog multipliers. The network is trained in a chipinloop fashion with a host computer implementing the training algorithm. The chip uses a serial digital weight bus implemented by a long shift register to input the weights. The inputs and outputs of the network are provided directly at pins on the chip. The training algorithm used is a parallel weight perturbation technique[1]. Training results are shown for a 2 input, 1 output network trained with an AND function, and for a 2 input, 2 hidden unit, 1 output network trained with an XOR function. 1.
Analog VLSI neural network with digital perturbative learning
 IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing
, 2002
"... [2] H. Fan, “A structural view of asymptotic convergence speed of adaptive ..."
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[2] H. Fan, “A structural view of asymptotic convergence speed of adaptive
unknown title
, 1999
"... Adaptive optics based on analog parallel stochastic optimization: analysis and experimental demonstration ..."
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Adaptive optics based on analog parallel stochastic optimization: analysis and experimental demonstration
I S
, 2001
"... First, I would like to thank my advisor, Rod Goodman, for providing me with the resources and tools necessary to produce this work. Next, I would like to thank the members of my thesis defense committee, Jehoshua Bruck, Christof Koch, Alain Martin, and Chris Diorio. I would also like to thank Petr V ..."
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First, I would like to thank my advisor, Rod Goodman, for providing me with the resources and tools necessary to produce this work. Next, I would like to thank the members of my thesis defense committee, Jehoshua Bruck, Christof Koch, Alain Martin, and Chris Diorio. I would also like to thank Petr Vogel for being on my candidacy committee. Thanks also goes out to some of my undergraduate professors, Andreas Andreou and Gert Cauwenberghs, for starting me off on this analog VLSI journey and for providing occasional guidance along the way. Many thanks go to the members of my lab and the Caltech VLSI community for fruitful conversations
1 A SiGe BiCMOS 8Channel MultiDithering, SubMicrosecond Adaptive Controller
"... Abstract — A SiGe BiCMOS mixedsignal adaptive controlleronchip is presented that implements gradient descent of a supplied analog control objective. Eight analog variables controlling the external plant are perturbed in parallel using sinusoidal dithers, and their gradient components are estimated ..."
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Abstract — A SiGe BiCMOS mixedsignal adaptive controlleronchip is presented that implements gradient descent of a supplied analog control objective. Eight analog variables controlling the external plant are perturbed in parallel using sinusoidal dithers, and their gradient components are estimated by parallel synchronous detection of the dithers in the control objective. Translinear allNPN bipolar circuits achieve linear tuning of frequency and amplitude in the oscillators and synchronous detectors, covering a 4kHz600MHz range in dither frequencies with30dB/octave suppression of intermodulation products. Experimental results demonstrate adaptive optimization of a 3variable nonlinear plant within 1µs, for dithers in the 100200MHz frequency range. The chip measures 3mm×3mm in 0.5µm SiGe and consumes 110mW at 3.3V supply. I.
neering and Electronics at The University of Edinburgh;
, 2006
"... Neuromorphic systems often call for subthreshold operation where transistor mismatch is a particular problem and this mismatch can affect the time constants of the design. This work is an investigation into whether Spike Timing Dependent Plasticity (STDP), a neural algorithm capable of adapting time ..."
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Neuromorphic systems often call for subthreshold operation where transistor mismatch is a particular problem and this mismatch can affect the time constants of the design. This work is an investigation into whether Spike Timing Dependent Plasticity (STDP), a neural algorithm capable of adapting time delays within neural systems, can provide a method to minimise the effect of transistor mismatch. This work is set within the context of a depthfrommotion algorithm, the performance of which will be degraded by mismatch when implemented in analogue VLSI. A circuit is designed which predicts the arrival of a spike from the timing of two earlier spikes. The error between the actual spike arrival time and the prediction is used to improve future predictions. Two spike timing dependent adaptation methods are described. These were fabricated using an Austria Microsystems (AMS) 0.35µm process and the results are reported. The key measure is the prediction error: before adaptation the error reflects the amount of mismatch within the prediction circuitry; after adaptation the error indicates to what extent the adaptive circuitry can minimise the effect of transistor mismatch. For both designs it is shown that the effect of transistor mismatch can be greatly reduced through spike timing dependent adaptation. I hereby declare that: Declaration of originality (a) the thesis has been composed entirely by myself; (b) the work is my own, except where clearly indicated, and originated in the School of Engi