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B.: Pipelined FPGA adders
 In: Field Programmable Logic and Applications. IEEE (2010
"... Abstract—Integer addition is a universal building block, and applications such as quadprecision floatingpoint or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the tradeoffs between size, latency and frequency for pipelined largeprecision adders on FPG ..."
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Abstract—Integer addition is a universal building block, and applications such as quadprecision floatingpoint or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the tradeoffs between size, latency and frequency for pipelined largeprecision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripplecarry adder, a variation that reduces register count, and an FPGAspecific implementation of the carryselect adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width. Keywordsaddition; pipeline; lowlatency; FPGA I.
AUTOMATIC GENERATION OF MODULAR MULTIPLIERS FOR FPGA APPLICATIONS 1 Automatic Generation of Modular Multipliers for FPGA Applications
"... Abstract — Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carrysave or borrowsave algori ..."
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Abstract — Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carrysave or borrowsave algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern Field Programmable Gate Arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a highradix carrysave number system, where a sum bit of the carrysave representation is replaced by a sum word. Two digits are then added by means of a small CarryRipple Adder (CRA). Furthermore, we propose an algorithm which selects the best highradix carrysave representation for a given modulus, and generates a synthesizable VHDL description of the operator. I.