A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M. In this article, we present a class of universal switch modules. Each of our switch modules has 6W switches and switch-module flexibility three (i.e., FS � 3). We prove that no switch module with less than 6W switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGAs and the antisymmetric switch modules (with FS � 3) 1 suggested by Rose and Brown [1991]. Although these two kinds of switch modules also have FS � 3 and 6W switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25 % more routing instances, compared with the XC4000-type switch module of the same size. Experimental results demonstrate that our universal switch modules improve routability at the chip level. Finally, our work also provides a theoretical insight into the important observation by Rose and Brown [1991] (based on extensive experiments) that FS � 3 is often sufficient to provide high routability.

A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (the number of nets on each side of M is at most W ) is simultaneously routable through M . In this paper, we present a class of universal switch modules. Each of our switch modules has 6W switches and switch-module flexibility three (FS = 3). We prove that no switch module with less than 6W switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGA's and the anti-symmetric switch modules (with FS = 3 1 ) suggested by [15]. Although these two kinds of switch modules also have FS = 3 and 6W switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the XC4000-type one of the same size. Experimental results demonstrate that our universal switch modules improve ro...

Switch modules are the most important component of the routing resources in FPGAs/FPICs. Previous works have shown that switch modules with higher routability result in better area performance for practical applications. We consider in this paper an FPGA/FPIC switch-module analysis problem: the inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. As a fundamental problem for the analysis of switch modules, this problem is applicable to the design and routability evaluation of FPGA/FPIC switch modules and FPGA/FPIC routing. We present a network-flow-based approximation algorithm for this problem. Based on mathematical analyses, we show that this algorithm has provably good performance with the bounds 5 and 5/4 away from the optima for two types of switch modules, respectively. Extensive experiments show that this algorithm is highly accurate

Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithms route one net at a time, and it can cause the netordering problem. In this paper, we present a detailed routing algorithm for FPGAs based on min-cost flow computations. Using the min-cost flow approach, our algorithm routes all the nets connected to a common logic module simultaneously. At each stage of the network flow computation, we guarantee optimal result in terms of routability and delay cost. For further improvement, we adopt an iterative refinement scheme based on the Lagrangian relaxation technique. The Lagrangian relaxation approach transforms the routing problem into a sequence of Lagrangian subproblems. At each iteration of the algorithm, Lagrangian subproblems are solved by our min-cost flow based routing algorithm. Any violation of congestion constraints is reflected in the value of corresponding Lagrangian multiplier. The Lagrangian multipliers are incorporated into the cost of each routing rosource node and guide the router. Because our min-cost flow based algorithm minimizes cost function while it maximizes the flow, our algorithm finds congestion-free routing solutions with minimum total delay. Comparison with VPR router shows that our router uses less or equal number of routing tracks with smaller critical path delay as well as total routing delay.

Field Programmable Gate Arrays (FPGAs) have become an increasingly useful and important architecture in hardware design. As a flexible alternative to custom integrated chips, FPGA-implemented designs can be produced quickly and cheaply. However, this flexibility comes at a significant performance penalty. To help address this issue, we propose a family of three-dimensional FPGA architectures, with increased speed and smaller size as compared to existing 2D FPGAs. We implemented the first suite of tools for creating circuit designs for the new proposed architecture, and used these tools to demonstrate the efficacy of 3D FPGAs (e.g., 3D FPGA circuit mappings seem superior to those mapped to 2D ones). We explored several issues arising in the design of both 2D and 3D- FPGAs, and implemented two useful tools: (1) Spiffy, which performs placement and global routing simultaneously for 2D and 3D FPGAs, and (2) Gambit, which is the first tool to perform placement, global routing and detailed routing simultaneously, and which demonstrates the usefulness of conflict graphs. These tools yield superior solutions within reasonable runtimes, and employ a "template smoothing" technique which significantly improves the results at a modest runtime cost. Our results indicate that 3D FPGAs are a viable future architecture.

The routing channels of today’s FPGAs consist of wire segments of various types, which allow the use of new techniques to enhance the routability of net segments in channels. In this paper we present an optimal greedy algorithm to switch the tracks that net segments are assigned to. This allows us to enhance the rerouting ability by capturing the features of the routing architecture. Suppose the number of tracks in the channels is given. The goal of this algorithm is to increase the number of routed segments of late rerouting requests. This is a good feature for supporting Engineering Change Order(ECO) type of routing. Supporting ECO routing enables the routing algorithms to deal with later changes in routing requests. We used the routing architecture of VirtexII FPGAs from Xilinx as our target architecture and integrated our algorithm into the VPR FPGA routing tool. The experimental results show that our algorithm makes VPR router capable of handling 28.4 % more rerouting for segments that are added to the design later.