We present an analysis of the benefits and drawbacks of function and object based models in system specification. Functional models should be used for functional design space exploration and as a functional reference model throughout all design and validation activities. Object based models should be used for architectural design space exploration and as a design specification for the following design and implementation phases. Thus, the question is not which one to adopt in system specification, but how to integrate them. We argue that the integration should be based on an explicit formulation of design decisions with a tool handling the consequences of the decisions. In this way a functional model can be transformed into an object based model efficiently and systematically and a discontinuity in the design process is avoided. We consider it important that the question of benefits of functional and object based models is decided by means of experiments. To this end we propose an experiment that would confirm or falsify our hypothesis. 1.

Introduction P. Marwedel 1 New, flexible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and in audio-, video-, and telecommunication-equipment. Essential advantages of these processors include their high flexibility, short design time and (in the case of off-the-shelf processors) full-custom layout quality. Furthermore, they allow an easy implementation of optional product features as well as easy design correction and upgrading. Furthermore, processors are frequently used in cases where the systems must be extremely dependable 1 [32]. In such cases, the re-use of the design of an off-the-shelf processor greatly simplifies dependability analysis. This contrasts with the limitations of application-specific circuits (ASICs): due to their low flexibility, the cost for the desig

This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on a limited set of templates that characterize the way data are exchanged between tasks realized either in software or in hardware. The templates are highly portable because their software part is implemented using the POSIX thread functions, and their hardware part is a hand crafted synthesizable module with a System VCI interface. These Interface Modules allow simple Virtual Component reuse since they not only implement protocol compatibility through the use of the System VCI/OCB standard but also system level communications through semantics widely accepted in the design community. 1.

This paper presents the development of a wireless communication system, the Long Range Identification Tag, built and tested in Heriot Watt University. The design commences in Spin, a high level model checking tool optimized for the verification of distributed systems. The abstract software model is synthesized automatically to HDL (Verilog/VHDL) and subsequently downloaded to the targeted FPGA platform. To enhance autonomous capacity of the device, run-time fault tolerance schemes such as watchdog timers and forward error correction routines are also developed. The wireless application is finally tested under a lab emulated EMI scheme and system survivability is examined and quantified. The principal objective of the paper and the associated research project (launched in 2002) is to investigate how a number of high-level reliability enhancement strategies can be utilized to promote more dependable embedded applications. 1.

The Lava system provides novel techniques for representing system level specifications which are supported by a design flow that maps Lava descriptions onto System-on-Chip platforms implemented on very large FPGAs. The key contribution of this paper is a type class based approach for specifying bus-based system configurations. This provides a very flexible and parameterised flow for combining predesigned IP blocks into a complete FPGA-based system.

In eingebetteten Systemen gibt es viele Anforderungen, die das Betriebssystem erfüllen muss. Diese reichen von stark

Abstract: Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model must only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools. 1.