We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.

Abstract—This paper presents a new physical theory of oscillator phase noise. Built around the concept of phase diffusion, this work bridges the fundamental physics of noise and existing oscillator phase-noise theories. The virtual damping of an ensemble of oscillators is introduced as a measure of phase noise. The explanation of linewidth compression through virtual damping provides a unified view of resonators and oscillators. The direct correspondence between phase noise and the Einstein relation is demonstrated, which reveals the underlying physics of phase noise. The validity of the new approach is confirmed by consistent experimental agreement. Index Terms—Analog integrated circuits, LC oscillators, oscillators, phase noise, radio-frequency (RF) circuits, resonators, ring oscillators. I.

A RF voltage-controlled oscillator (VCO) employs an on-chip, high-Q, three-dimensional (3-D) coil inductor and micro-machined variable capacitor for frequency tuning. Unlike con-ventional spiral inductors, the 3-D inductor minimizes the substrate loss and achieves a record Q of 30 at 1 GHz. The micromachined variable capacitor achieves a 15 % tuning range with a nominal 2pF capacitance and a Q value above 60 at 1 GHz. Both passive components are fabricated on silicon sub-strates and thus amenable to monolithic integration with stan-dard IC processes. The prototype VCO exhibits a phase-noise of- 136 dBcMz at 3 MHz offset frequency from the carrier, suit-able for most wireless communication applications, in particular GSM [l]. The VCO is tunable from 8.55 MHz to 863 MHz under 3V, limited by the test setup.

voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of I noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency. Index Terms—Energy-efficient, energy model, peak-to-mean ratio (PAR), pulse shaping roll-off factor, RF front-end. I.

Abstract—A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of 22 dBm, and larger than 70 dB local-oscillator–RF isolation. The phase noise of the on-chip VCO is 100 and 128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is C10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply. Index Terms — Clock distribution network, image-reject-filter, inductors, low-noise amplifier, mixer, resonators, SiGe HBT,

at both the architecture and the circuit level. The high center This paper describes the design of CMOS a frequency synfrequency of the voltage-controlled oscillator (VCO), the poor thesizer targeting wireless local area network applications quality of inductors due to skin effect and substrate loss, the in the 5-GHz range. Based on an integer-N architecture, limited tuning range, the nonlinearity of the VCO inputloutput the synthesizer produces a 5.2-GHz output as well as the characteristic, the high speed required of the dual-modulus quadrature phases of a 2.6-GHz carrier. Fabricated in a divider, the mismatches in the charge pump, and the imple-0.4-pm digital CMOS technology, the circuit provides a mentation of the loop filter are among the issues encountered channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of-115 dBdHz at 2.6 GHz and-100 dBdHz in this design. In order to relax some of the synthesizer requirements, the at 5.2 GHz at 10-MHz offset. The reference sidebands are transceiver and the synthesizer have been designed concurat-50 dBc at 2.6 GHz and the power dissipation from a rently. Fig. 1 shows the transceiver architecture [2] and 2.6-V supply is 47 mW. I.

Abstract—This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer- architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4- m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of 115 dBc/Hz at 2.6 GHz and 100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at 53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW. Index Terms—Frequency dividers, oscillators, phase-locked loops, RF circuits, synthesizers, wireless transceivers.

Abstract—The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power requirements of large digital circuits also yield significant advantages for analog applications. The reverse thickness scaling of the top metal layer can be exploited in the design of low-loss transmission lines. Coplanar transmission lines in the top metal layers take advantage of a low metal resistance and a large separation from the heavily doped silicon substrate. They are therefore fully compatible with current and future CMOS process technologies. To investigate the feasibility of extending CMOS designs beyond 10 GHz, a wide range of coplanar transmission lines are characterized. The effect of the substrate resistivity on coplanar wave propagation is explained. After achieving a record loss of 0.3 dB/mm at 50 GHz, coplanar lines are used in the design of distributed amplifiers and oscillators. They are the first to achieve higher than 10-GHz operating frequencies in a conventional CMOS technology. Index Terms—CMOS integrated circuits, interconnections, microwave integrated circuits, oscillators, transmission lines, traveling wave amplifiers. I.

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35- m MOS transistors. The measured phase-noise values are 121, 117, and 115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.

... frequency communication systems. They are used for carrier frequency synthesis to up- and down-convert signMs. This work presents a fully integrated 5 GHz VCO designed for the 0.25 /m IBM BiCMOS6HP process using only CMOS devices. The design is suitable for the usage in a phase-locked loop (PLL). It is amenable for future technologies and allows easy porting to different CMOS manufacturing processes. This is accomplished by the implementation of a VCO design methodology in a Maple worksheet that allows to rapidly design a NMOS-PMOS cross-coupled LC VCO for a given technology specification and given performance figures such as the tuning range or the power consumption. The design methodology enables "design by spreadsheet" and allows to easily trade the different performance figures against one another. Further design aids are provided for the design of maximum-Q inductors and varactors. Using this design methodology, a fully integrated 5 GHz CMOS VCO is implemented for the 0.25/m IBM BiCMOS6HP process on the schematic-layer in Cadence. The VCO employs patterned silicided ground shield inductors with an estimated Q of 12.18 and inversion NMOS-varactors. It features a supply voltage of 2.5 V, a core current of only 1.15 mA, and a monotone f(Vco**t)-characteristic. The frequency is tunable between 4.39 GHz and 5.62 GHz which corresponds to a tuning range of 24.6 %.