Abstract—We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented either as on-chip hardware or through presimulated and stored test data. In either case a handshake protocol controls the rate of test data flow between the automatic test equipment (ATE) and device under test (DUT). The test time reduction accomplished depends upon an average activity factor α. For low α, about 50 % test time reduction is analytically shown. With moderate activity, α = 0.5, simulated test data gives about 25 % test time reduction for ITC02 benchmarks. For full scan s38584, the dynamic scan clock control reduced the test time by 19 % when fully specified ATPG vectors were used and by 43 % for vectors with don’t cares. BIST with dynamic clock showed about 19 % test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3 % hardware overhead. Index Terms—Scan test, test time reduction, test power, onchip activity monitor, adaptive test clock I.

We reduce the test time of external test applied from an automatic test equipment (ATE) by speeding up low activity cycles without exceeding the specified peak power budget. An activity monitor is implemented as hardware or as presimulated and stored test data for this purpose. The achieved test time reduction depends upon the input and output activity factors,αin andαout, of the scan chain. When on-circuit built-in hardware control is used, test time reductions of about 50 % and 25 % are possible for vectors with low input activity (αin ≈ 0) and moderate input activity (αin = 0.5), respectively, in ITC02 benchmark circuits. When stored pre-simulated test data is used, test time reduction of up to 99 % is shown for vectors with low input and output activities.

Abstract—We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented as on-chip hardware. Two models, one for test sets with peak activity factor of 1 and the other for test sets with peak activity factor lower than 1 have been proposed. In test sets with peak activity factors of 1, the test time reduction accomplished depends upon an average activity factor ofαin. For low αin, about 50 % test time reduction is analytically shown. With moderate activity, αin = 0.5, simulated test data gives about 25 % test time reduction for ITC02 benchmarks. BIST with dynamic clock showed about 19 % test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3 % hardware overhead. In test sets with peak activity factors lower than 1, the test time reduction depends on an input activity factor of αin and an output activity factor of αout. For low αin and high αout, a test time reduction of about 50 % is analytically shown. Index Terms—Scan test, test time reduction, test power, onchip activity monitor, adaptive test clock, activity factor, BIST I.

In recent years, circuit size has increased due to scaling down of technology. Controlling power dissipation in these large circuits during test sessions is one of the major concerns in VLSItesting. In generalpower dissipation ofasystem in test modeishigherthanthenormal mode. This extra power can cause problems such as instantaneous power surge that causes circuit damage, formation of hot spots, difficulty in performance verification and reduction of system lifetime and product yield. The reason behind the high power dissipation during test is because unlike normal mode operation of the system correlation between consecutive test patterns does not exist in test mode. This is particularly true in case of Built-In-Self-Test (BIST) and scan-Based BIST, two popular DFT methodologies. To increase the correlation between consecutive vectors during testing, several techniques have been proposed for creating low transition density in the pattern sets and thus control the power dissipation. However, this in turn increases the test application time as the test has to run for longer test sessions to reach sufficient fault coverage. Increase in test time is undesirable as testing cost of a chip is directly related to the time it takes to test the chip. This