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Lazy Man’s Logic Synthesis
"... Abstract — Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy” approach to logic synthesis based on the f ..."
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Abstract — Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy” approach to logic synthesis based on the following observations: (a) optimal or nearoptimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a casestudy shows that logic level minimization using lazy man’s synthesis improves delay after LUT mapping into 4 and 6input LUTs, compared to earlier work on higheffort delay optimization. I.
Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power
 in Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA'12
"... FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circui ..."
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FPGA CAD algorithms are heuristic, and generally make use of cost functions to gauge the value of one potential circuit implementation over another. At times, such algorithms must decide between two or more implementation options of apparently equal cost. This work explores the variations in circuit quality, i.e. noise, that arise when CAD algorithms are altered to choose randomly when faced with such equalcost alternatives. Noise sources are identified in logic synthesis and technology mapping algorithms, and experimental results are presented which show standard deviations of 3.3 % and 3.7 % from the mean in postrouted delay and power. As a means of dealing with this variation, early timing and power prediction metrics can be applied after technology mapping to find the best circuits in the presence of noise. When applied to designs with over 1.5 % variation in delay and power, the best prediction models have a 40% probability of capturing the best circuit when predicting the top 10 % of circuits in a group of noiseinjected circuits.
A Tight Consistent Delay Model for Black Boxes
"... A Boolean network with unknown components can be modeled as an AIG with black boxes (bbAIG). The delay of an AIG is measured in terms of its maximum level after it is balanced. We propose a delay model for a black box which is consistent in that if a bbAIG is refined by replacing an internal black ..."
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A Boolean network with unknown components can be modeled as an AIG with black boxes (bbAIG). The delay of an AIG is measured in terms of its maximum level after it is balanced. We propose a delay model for a black box which is consistent in that if a bbAIG is refined by replacing an internal black box with another bbAIG, its delay cannot decrease. It is also tight in that there exists an AIG which can replace a black box resulting in a delay equal to the estimated one. We prove that the proposed black box delay estimation is consistent and tight. 1
Enumeration of Irredundant Circuit Structures
"... A new approach to Boolean decomposition and matching is proposed. It uses enumeration of all supportreducing decompositions of Boolean functions up to 16 inputs. The approach is implemented in a new framework that compactly stores multiple circuit structures. The method makes use of precomputation ..."
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A new approach to Boolean decomposition and matching is proposed. It uses enumeration of all supportreducing decompositions of Boolean functions up to 16 inputs. The approach is implemented in a new framework that compactly stores multiple circuit structures. The method makes use of precomputations performed offline, before the framework is started by the calling application. As a result, the runtime of the online computations is substantially reduced. For example, matching Boolean functions against an interconnected LUT structure during technology mapping is reduced to the extent that it no longer dominates the runtime of the mapper. Experimental results indicate that this work has promising applications in CAD tools for both FPGAs and standard cells. 1.